amd/mendocino: Control DPTC with only Kconfig
SOC_AMD_COMMON_BLOCK_ACPI_DPTC can be enabled conditionally for any skyrim boards, similar to mainboard/google/zork/Kconfig. This makes the value dptc_tablet_mode_enable redundant. This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC is only included for boards that actually enable it. BRANCH=none BUG=b:217911928 TEST=emerge-skyrim coreboot Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I73fca5a16826313219247f452d37fb526ad4f4df Reviewed-on: https://review.coreboot.org/c/coreboot/+/67639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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@ -82,8 +82,6 @@ struct soc_amd_mendocino_config {
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uint32_t telemetry_vddcrsocfull_scale_current_mA;
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uint32_t telemetry_vddcrsocoffset;
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bool dptc_enable;
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/* The array index is the general purpose PCIe clock output number. Values in here
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aren't the values written to the register to have the default to be always on. */
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enum {
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@ -188,10 +188,7 @@ static void acipgen_dptci(void)
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{
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const struct soc_amd_mendocino_config *config = config_of_soc();
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if (!config->dptc_enable)
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return;
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/* DPTC is enabled. Always fill out the default DPTC values. */
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/* Normal mode DPTC values. */
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struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC,
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config->sustained_power_limit_mW,
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config->fast_ppt_limit_mW,
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@ -202,7 +199,8 @@ static void acipgen_dptci(void)
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static void root_complex_fill_ssdt(const struct device *device)
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{
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acpi_fill_root_complex_tom(device);
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acipgen_dptci();
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if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC))
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acipgen_dptci();
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}
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static const char *gnb_acpi_name(const struct device *dev)
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