GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

amd/mendocino: Control DPTC with only Kconfig 

SOC_AMD_COMMON_BLOCK_ACPI_DPTC can be enabled conditionally for any
skyrim boards, similar to mainboard/google/zork/Kconfig. This makes the
value dptc_tablet_mode_enable redundant.

This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely
with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC
is only included for boards that actually enable it.

BRANCH=none
BUG=b:217911928
TEST=emerge-skyrim coreboot

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I73fca5a16826313219247f452d37fb526ad4f4df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Tim Van Patten 2022-09-13 15:42:01 -06:00 committed by Felix Held
parent 9eac097205
commit 53ba14de1e
2 changed files with 3 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/amd/mendocino/chip.h
View File

@ -82,8 +82,6 @@ struct soc_amd_mendocino_config {
uint32_t telemetry_vddcrsocfull_scale_current_mA; uint32_t telemetry_vddcrsocfull_scale_current_mA;
uint32_t telemetry_vddcrsocoffset; uint32_t telemetry_vddcrsocoffset;
bool dptc_enable;
/* The array index is the general purpose PCIe clock output number. Values in here /* The array index is the general purpose PCIe clock output number. Values in here
aren't the values written to the register to have the default to be always on. */ aren't the values written to the register to have the default to be always on. */
enum { enum {

6
src/soc/amd/mendocino/root_complex.c
View File

@ -188,10 +188,7 @@ static void acipgen_dptci(void)
{ {
const struct soc_amd_mendocino_config *config = config_of_soc(); const struct soc_amd_mendocino_config *config = config_of_soc();
if (!config->dptc_enable) /* Normal mode DPTC values. */
return;
/* DPTC is enabled. Always fill out the default DPTC values. */
struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC, struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC,
config->sustained_power_limit_mW, config->sustained_power_limit_mW,
config->fast_ppt_limit_mW, config->fast_ppt_limit_mW,
@ -202,6 +199,7 @@ static void acipgen_dptci(void)
static void root_complex_fill_ssdt(const struct device *device) static void root_complex_fill_ssdt(const struct device *device)
{ {
acpi_fill_root_complex_tom(device); acpi_fill_root_complex_tom(device);
if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC))
acipgen_dptci(); acipgen_dptci();
} }