drv/intel/gma/opregion: Add common init_idg_opregion()
Add a new common method to initialize ACPI OpRegion. * Try to locate vbt.bin in CBFS. * Try to locate VBIOS in CBFS. * Keep existing code to probe at 0xc0000. Tested on Lenovo T430 (sandybridge) using vbt.bin, tested using buggy VBIOS with wrong vbt_offset, tested with fake vbt written by NGI at 0xc0000. Tested with https://review.coreboot.org/#/c/21766/ on i945 (using fake vbt at 0xc0000), x4x (using vbt.bin) and gm45 (using vendor VBIOS). In all cases linux was successfully provided with VBT from ACPI opregion. Change-Id: I8ee50ea9900537bd9e3ca5ab0cd3f48d2acec970 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Matt DeVillier
Patrick Rudolph
parent
74145f7615
commit
53e4195625
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@ -17,6 +17,7 @@
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#include <arch/acpi.h>
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#include <types.h>
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#include <string.h>
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#include <cbfs.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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@ -67,70 +68,195 @@ void intel_gma_restore_opregion(void)
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}
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}
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static void *get_intel_vbios(void)
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static enum cb_err vbt_validate(struct region_device *rdev)
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{
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/* This should probably be looking at CBFS or we should always
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* deploy the VBIOS on Intel systems, even if we don't run it
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* in coreboot (e.g. SeaBIOS only scenarios).
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*/
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u8 *vbios = (u8 *)0xc0000;
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uint32_t sig;
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optionrom_header_t *oprom = (optionrom_header_t *)vbios;
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optionrom_pcir_t *pcir = (optionrom_pcir_t *)(vbios +
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oprom->pcir_offset);
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printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n",
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oprom->signature, pcir->vendor, pcir->classcode[0],
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pcir->classcode[1], pcir->classcode[2]);
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if ((oprom->signature == OPROM_SIGNATURE) &&
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(pcir->vendor == PCI_VENDOR_ID_INTEL) &&
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(pcir->classcode[0] == 0x00) &&
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(pcir->classcode[1] == 0x00) &&
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(pcir->classcode[2] == 0x03))
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return (void *)vbios;
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return NULL;
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}
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static enum cb_err init_opregion_vbt(igd_opregion_t *opregion)
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{
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void *vbios;
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vbios = get_intel_vbios();
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if (!vbios) {
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printk(BIOS_DEBUG, "VBIOS not found.\n");
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if (rdev_readat(rdev, &sig, 0, sizeof(sig)) != sizeof(sig))
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return CB_ERR;
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}
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printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios);
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optionrom_header_t *oprom = (optionrom_header_t *)vbios;
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optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
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oprom->vbt_offset);
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if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
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printk(BIOS_DEBUG, "VBT not found!\n");
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if (sig != VBT_SIGNATURE)
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return CB_ERR;
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}
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memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
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memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ?
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vbt->hdr_vbt_size : 7168);
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return CB_SUCCESS;
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}
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/* Initialize IGD OpRegion, called from ACPI code and OS drivers */
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enum cb_err intel_gma_init_igd_opregion(igd_opregion_t *opregion)
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static enum cb_err locate_vbt_vbios(const u8 *vbios, struct region_device *rdev)
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{
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const optionrom_header_t *oprom;
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const optionrom_pcir_t *pcir;
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struct region_device rd;
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enum cb_err ret;
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u8 opromsize;
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size_t offset;
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memset((void *)opregion, 0, sizeof(igd_opregion_t));
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// FIXME: caller should supply a region_device instead of vbios pointer
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if (rdev_chain(&rd, &addrspace_32bit.rdev, (uintptr_t)vbios,
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sizeof(*oprom)))
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return CB_ERR;
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// FIXME if IGD is disabled, we should exit here.
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if (rdev_readat(&rd, &opromsize, offsetof(optionrom_header_t, size),
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sizeof(opromsize)) != sizeof(opromsize) || !opromsize)
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return CB_ERR;
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if (rdev_chain(&rd, &addrspace_32bit.rdev, (uintptr_t)vbios,
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opromsize * 512))
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return CB_ERR;
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oprom = rdev_mmap(&rd, 0, sizeof(*oprom));
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if (!oprom)
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return CB_ERR;
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if (!oprom->pcir_offset || !oprom->vbt_offset) {
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rdev_munmap(&rd, (void *)oprom);
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return CB_ERR;
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}
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pcir = rdev_mmap(&rd, oprom->pcir_offset, sizeof(*pcir));
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if (pcir == NULL) {
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rdev_munmap(&rd, (void *)oprom);
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return CB_ERR;
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}
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printk(BIOS_DEBUG, "GMA: locate_vbt_vbios: %x %x %x %x %x\n",
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oprom->signature, pcir->vendor, pcir->classcode[0],
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pcir->classcode[1], pcir->classcode[2]);
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/* Make sure we got an Intel VGA option rom */
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if ((oprom->signature != OPROM_SIGNATURE) ||
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(pcir->vendor != PCI_VENDOR_ID_INTEL) ||
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(pcir->signature != 0x52494350) ||
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(pcir->classcode[0] != 0x00) ||
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(pcir->classcode[1] != 0x00) ||
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(pcir->classcode[2] != 0x03)) {
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rdev_munmap(&rd, (void *)oprom);
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rdev_munmap(&rd, (void *)pcir);
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return CB_ERR;
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}
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rdev_munmap(&rd, (void *)pcir);
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/* Search for $VBT as some VBIOS are broken... */
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offset = oprom->vbt_offset;
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do {
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ret = rdev_chain(rdev, &rd, offset,
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(opromsize * 512) - offset);
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offset++;
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} while (ret == CB_SUCCESS && vbt_validate(rdev) != CB_SUCCESS);
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offset--;
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if (ret == CB_SUCCESS && offset != oprom->vbt_offset)
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printk(BIOS_WARNING, "GMA: Buggy VBIOS found\n");
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else if (ret != CB_SUCCESS)
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printk(BIOS_ERR, "GMA: Broken VBIOS found\n");
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rdev_munmap(&rd, (void *)oprom);
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return ret;
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}
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static enum cb_err locate_vbt_cbfs(struct region_device *rdev)
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{
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struct cbfsf file_desc;
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/* try to locate vbt.bin in CBFS */
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if (cbfs_boot_locate(&file_desc, "vbt.bin", NULL) == CB_SUCCESS) {
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cbfs_file_data(rdev, &file_desc);
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printk(BIOS_INFO, "GMA: Found VBT in CBFS\n");
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return CB_SUCCESS;
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}
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return CB_ERR;
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}
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static enum cb_err locate_vbt_vbios_cbfs(struct region_device *rdev)
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{
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const u8 *oprom =
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(const u8 *)pci_rom_probe(dev_find_slot(0, PCI_DEVFN(0x2, 0)));
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if (oprom == NULL)
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return CB_ERR;
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printk(BIOS_INFO, "GMA: Found VBIOS in CBFS\n");
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return locate_vbt_vbios(oprom, rdev);
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}
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/* Initialize IGD OpRegion, called from ACPI code and OS drivers */
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enum cb_err
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intel_gma_init_igd_opregion(igd_opregion_t *opregion)
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{
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struct region_device rdev;
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optionrom_vbt_t *vbt = NULL;
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optionrom_vbt_t *ext_vbt;
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bool found = false;
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/* Search for vbt.bin in CBFS. */
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if (locate_vbt_cbfs(&rdev) == CB_SUCCESS &&
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vbt_validate(&rdev) == CB_SUCCESS) {
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found = true;
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printk(BIOS_INFO, "GMA: Found valid VBT in CBFS\n");
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}
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/* Search for pci8086,XXXX.rom in CBFS. */
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else if (locate_vbt_vbios_cbfs(&rdev) == CB_SUCCESS &&
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vbt_validate(&rdev) == CB_SUCCESS) {
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found = true;
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printk(BIOS_INFO, "GMA: Found valid VBT in VBIOS\n");
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}
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/*
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* Try to locate Intel VBIOS at 0xc0000. It might have been placed by
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* Native Graphics Init as fake Option ROM or when coreboot did run the
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* VBIOS on legacy platforms.
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* TODO: Place generated fake VBT in CBMEM and get rid of this.
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*/
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else if (locate_vbt_vbios((u8 *)0xc0000, &rdev) == CB_SUCCESS &&
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vbt_validate(&rdev) == CB_SUCCESS) {
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found = true;
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printk(BIOS_INFO, "GMA: Found valid VBT in legacy area\n");
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}
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if (!found) {
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printk(BIOS_ERR, "GMA: VBT couldn't be found\n");
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return CB_ERR;
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}
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vbt = rdev_mmap_full(&rdev);
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if (!vbt) {
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printk(BIOS_ERR, "GMA: Error mapping VBT\n");
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return CB_ERR;
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}
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if (vbt->hdr_vbt_size > region_device_sz(&rdev)) {
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printk(BIOS_ERR, "GMA: Error mapped only a partial VBT\n");
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rdev_munmap(&rdev, vbt);
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return CB_ERR;
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}
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memset(opregion, 0, sizeof(igd_opregion_t));
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memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
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sizeof(opregion->header.signature));
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memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild,
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ARRAY_SIZE(vbt->coreblock_biosbuild));
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/* Extended VBT support */
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if (vbt->hdr_vbt_size > sizeof(opregion->vbt.gvd1)) {
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ext_vbt = cbmem_add(CBMEM_ID_EXT_VBT, vbt->hdr_vbt_size);
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if (ext_vbt == NULL) {
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printk(BIOS_ERR,
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"GMA: Unable to add Ext VBT to cbmem!\n");
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rdev_munmap(&rdev, vbt);
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return CB_ERR;
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}
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memcpy(ext_vbt, vbt, vbt->hdr_vbt_size);
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opregion->mailbox3.rvda = (uintptr_t)ext_vbt;
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opregion->mailbox3.rvds = vbt->hdr_vbt_size;
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} else {
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/* Raw VBT size which can fit in gvd1 */
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memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size);
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}
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rdev_munmap(&rdev, vbt);
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/* 8kb */
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opregion->header.size = sizeof(igd_opregion_t) / 1024;
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@ -158,10 +284,6 @@ enum cb_err intel_gma_init_igd_opregion(igd_opregion_t *opregion)
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opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
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opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
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ret = init_opregion_vbt(opregion);
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if (ret != CB_SUCCESS)
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return ret;
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/* Write ASLS PCI register and prepare SWSCI register. */
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intel_gma_opregion_register((uintptr_t)opregion);
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