intel/baytrail,braswell,broadwell: Add const qualifier for power_state

Change-Id: I37781c1423b49130ffd0d5f9fbdd28a36c9c6179
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/intel/baytrail/romstage/romstage.c

@@ -59,7 +59,7 @@ static struct chipset_power_state *fill_power_state(void)
 }
 
 /* Return 0, 3, or 5 to indicate the previous sleep state. */
-static int chipset_prev_sleep_state(struct chipset_power_state *ps)
+static int chipset_prev_sleep_state(const struct chipset_power_state *ps)
 {
 	/* Default to S0. */
 	int prev_sleep_state = ACPI_S0;

src/soc/intel/braswell/include/soc/romstage.h

@@ -11,7 +11,7 @@ void gfx_init(void);
 void punit_init(void);
 
 /* romstage.c functions */
-int chipset_prev_sleep_state(struct chipset_power_state *ps);
+int chipset_prev_sleep_state(const struct chipset_power_state *ps);
 
 /* Values for FSP's PcdMemoryTypeEnable */
 #define MEM_DDR3	0

src/soc/intel/braswell/romstage/romstage.c

@@ -57,7 +57,7 @@ struct chipset_power_state *fill_power_state(void)
 }
 
 /* Return 0, 3, or 5 to indicate the previous sleep state. */
-int chipset_prev_sleep_state(struct chipset_power_state *ps)
+int chipset_prev_sleep_state(const struct chipset_power_state *ps)
 {
 	/* Default to S0. */
 	int prev_sleep_state = ACPI_S0;

src/soc/intel/broadwell/pch/power_state.c

@@ -33,7 +33,7 @@ static void migrate_power_state(int is_recovery)
 ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state)
 
 /* Return 0, 3, or 5 to indicate the previous sleep state. */
-static int prev_sleep_state(struct chipset_power_state *ps)
+static int prev_sleep_state(const struct chipset_power_state *ps)
 {
 	/* Default to S0. */
 	int prev_sleep_state = ACPI_S0;