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exynos5420: Replace the 5250 clock logic with 5420. 

The new code is stolen from U-Boot with little or no understanding of how it
works.

Change-Id: I3de7d25174072f6068d9d4fdaa308c0462296737
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3658
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Gabe Black 2013-05-17 11:29:22 -07:00 committed by Stefan Reinauer
parent 99ed2a83b5
commit 5420e09131
5 changed files with 1175 additions and 1053 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1189
src/cpu/samsung/exynos5420/clk.h
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File diff suppressed because it is too large Load Diff

190
src/cpu/samsung/exynos5420/clock.c
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@ -28,100 +28,6 @@
/* input clock of PLL: SMDK5420 has 24MHz input clock */ /* input clock of PLL: SMDK5420 has 24MHz input clock */
#define CONFIG_SYS_CLK_FREQ 24000000 #define CONFIG_SYS_CLK_FREQ 24000000
static struct arm_clk_ratios arm_clk_ratios[] = {
{
.arm_freq_mhz = 600,
.apll_mdiv = 0xc8,
.apll_pdiv = 0x4,
.apll_sdiv = 0x1,
.arm2_ratio = 0x0,
.apll_ratio = 0x1,
.pclk_dbg_ratio = 0x1,
.atb_ratio = 0x2,
.periph_ratio = 0x7,
.acp_ratio = 0x7,
.cpud_ratio = 0x1,
.arm_ratio = 0x0,
}, {
.arm_freq_mhz = 800,
.apll_mdiv = 0x64,
.apll_pdiv = 0x3,
.apll_sdiv = 0x0,
.arm2_ratio = 0x0,
.apll_ratio = 0x1,
.pclk_dbg_ratio = 0x1,
.atb_ratio = 0x3,
.periph_ratio = 0x7,
.acp_ratio = 0x7,
.cpud_ratio = 0x2,
.arm_ratio = 0x0,
}, {
.arm_freq_mhz = 1000,
.apll_mdiv = 0x7d,
.apll_pdiv = 0x3,
.apll_sdiv = 0x0,
.arm2_ratio = 0x0,
.apll_ratio = 0x1,
.pclk_dbg_ratio = 0x1,
.atb_ratio = 0x4,
.periph_ratio = 0x7,
.acp_ratio = 0x7,
.cpud_ratio = 0x2,
.arm_ratio = 0x0,
}, {
.arm_freq_mhz = 1200,
.apll_mdiv = 0x96,
.apll_pdiv = 0x3,
.apll_sdiv = 0x0,
.arm2_ratio = 0x0,
.apll_ratio = 0x3,
.pclk_dbg_ratio = 0x1,
.atb_ratio = 0x5,
.periph_ratio = 0x7,
.acp_ratio = 0x7,
.cpud_ratio = 0x3,
.arm_ratio = 0x0,
}, {
.arm_freq_mhz = 1400,
.apll_mdiv = 0xaf,
.apll_pdiv = 0x3,
.apll_sdiv = 0x0,
.arm2_ratio = 0x0,
.apll_ratio = 0x3,
.pclk_dbg_ratio = 0x1,
.atb_ratio = 0x6,
.periph_ratio = 0x7,
.acp_ratio = 0x7,
.cpud_ratio = 0x3,
.arm_ratio = 0x0,
}, {
.arm_freq_mhz = 1700,
.apll_mdiv = 0x1a9,
.apll_pdiv = 0x6,
.apll_sdiv = 0x0,
.arm2_ratio = 0x0,
.apll_ratio = 0x3,
.pclk_dbg_ratio = 0x1,
.atb_ratio = 0x6,
.periph_ratio = 0x7,
.acp_ratio = 0x7,
.cpud_ratio = 0x3,
.arm_ratio = 0x0,
}
};
/* src_bit div_bit prediv_bit */ /* src_bit div_bit prediv_bit */
static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
{0, 4, 0, -1}, {0, 4, 0, -1},
@ -173,8 +79,8 @@ static struct st_epll_con_val epll_div[] = {
/* exynos5: return pll clock frequency */ /* exynos5: return pll clock frequency */
unsigned long get_pll_clk(int pllreg) unsigned long get_pll_clk(int pllreg)
{ {
struct exynos5_clock *clk = struct exynos5420_clock *clk =
samsung_get_base_clock(); (struct exynos5420_clock *)samsung_get_base_clock();
unsigned long r, m, p, s, k = 0, mask, fout; unsigned long r, m, p, s, k = 0, mask, fout;
unsigned int freq; unsigned int freq;
@ -182,9 +88,6 @@ unsigned long get_pll_clk(int pllreg)
case APLL: case APLL:
r = readl(&clk->apll_con0); r = readl(&clk->apll_con0);
break; break;
case BPLL:
r = readl(&clk->bpll_con0);
break;
case MPLL: case MPLL:
r = readl(&clk->mpll_con0); r = readl(&clk->mpll_con0);
break; break;
@ -196,6 +99,16 @@ unsigned long get_pll_clk(int pllreg)
r = readl(&clk->vpll_con0); r = readl(&clk->vpll_con0);
k = readl(&clk->vpll_con1); k = readl(&clk->vpll_con1);
break; break;
case BPLL:
r = readl(&clk->bpll_con0);
break;
case RPLL:
r = readl(&clk->rpll_con0);
k = readl(&clk->rpll_con1);
break;
case SPLL:
r = readl(&clk->spll_con0);
break;
default: default:
printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg); printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg);
return 0; return 0;
@ -207,7 +120,8 @@ unsigned long get_pll_clk(int pllreg)
* EPLL_CON: MIDV [24:16] * EPLL_CON: MIDV [24:16]
* VPLL_CON: MIDV [24:16] * VPLL_CON: MIDV [24:16]
*/ */
if (pllreg == APLL || pllreg == BPLL || pllreg == MPLL) if (pllreg == APLL || pllreg == BPLL || pllreg == MPLL ||
pllreg == SPLL)
mask = 0x3ff; mask = 0x3ff;
else else
mask = 0x1ff; mask = 0x1ff;
@ -221,7 +135,7 @@ unsigned long get_pll_clk(int pllreg)
freq = CONFIG_SYS_CLK_FREQ; freq = CONFIG_SYS_CLK_FREQ;
if (pllreg == EPLL) { if (pllreg == EPLL || pllreg == RPLL) {
k = k & 0xffff; k = k & 0xffff;
/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
fout = (m + k / 65536) * (freq / (p * (1 << s))); fout = (m + k / 65536) * (freq / (p * (1 << s)));
@ -239,11 +153,10 @@ unsigned long get_pll_clk(int pllreg)
unsigned long clock_get_periph_rate(enum periph_id peripheral) unsigned long clock_get_periph_rate(enum periph_id peripheral)
{ {
struct exynos5_clock *clk =
samsung_get_base_clock();
struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
unsigned long sclk, sub_clk; unsigned long sclk, sub_clk;
unsigned int src, div, sub_div; unsigned int src, div, sub_div;
struct exynos5_clock *clk = samsung_get_base_clock();
switch (peripheral) { switch (peripheral) {
case PERIPH_ID_UART0: case PERIPH_ID_UART0:
@ -275,10 +188,6 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
src = readl(&clk->sclk_src_isp); src = readl(&clk->sclk_src_isp);
div = readl(&clk->sclk_div_isp); div = readl(&clk->sclk_div_isp);
break; break;
case PERIPH_ID_SATA:
src = readl(&clk->src_fsys);
div = readl(&clk->div_fsys0);
break;
case PERIPH_ID_SDMMC0: case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC2: case PERIPH_ID_SDMMC2:
@ -303,26 +212,27 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
return -1; return -1;
}; };
src = (src >> bit_info->src_bit) & ((1 << bit_info->n_src_bits) - 1); src = (src >> bit_info->src_bit) & 0xf;
if (peripheral == PERIPH_ID_SATA) {
if (src) switch (src) {
sclk = get_pll_clk(BPLL); case EXYNOS_SRC_MPLL:
else
sclk = get_pll_clk(MPLL); sclk = get_pll_clk(MPLL);
} else { break;
if (src == SRC_MPLL) case EXYNOS_SRC_EPLL:
sclk = get_pll_clk(MPLL);
else if (src == SRC_EPLL)
sclk = get_pll_clk(EPLL); sclk = get_pll_clk(EPLL);
else if (src == SRC_VPLL) break;
case EXYNOS_SRC_VPLL:
sclk = get_pll_clk(VPLL); sclk = get_pll_clk(VPLL);
else break;
default:
return 0; return 0;
} }
/* Ratio clock division for this peripheral */
sub_div = (div >> bit_info->div_bit) & 0xf; sub_div = (div >> bit_info->div_bit) & 0xf;
sub_clk = sclk / (sub_div + 1); sub_clk = sclk / (sub_div + 1);
/* Pre-ratio clock division for SDMMC0 and 2 */
if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) { if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
div = (div >> bit_info->prediv_bit) & 0xff; div = (div >> bit_info->prediv_bit) & 0xff;
return sub_clk / (div + 1); return sub_clk / (div + 1);
@ -334,8 +244,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
/* exynos5: return ARM clock frequency */ /* exynos5: return ARM clock frequency */
unsigned long get_arm_clk(void) unsigned long get_arm_clk(void)
{ {
struct exynos5_clock *clk = struct exynos5_clock *clk = samsung_get_base_clock();
samsung_get_base_clock();
unsigned long div; unsigned long div;
unsigned long armclk; unsigned long armclk;
unsigned int arm_ratio; unsigned int arm_ratio;
@ -353,45 +262,20 @@ unsigned long get_arm_clk(void)
return armclk; return armclk;
} }
struct arm_clk_ratios *get_arm_clk_ratios(void)
{
struct arm_clk_ratios *arm_ratio;
unsigned long arm_freq = 1700; /* FIXME: use get_arm_clk() */
int i;
for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
i++, arm_ratio++) {
if (arm_ratio->arm_freq_mhz == arm_freq)
return arm_ratio;
}
return NULL;
}
/* exynos5: set the mmc clock */ /* exynos5: set the mmc clock */
void set_mmc_clk(int dev_index, unsigned int div) void set_mmc_clk(int dev_index, unsigned int div)
{ {
struct exynos5_clock *clk = struct exynos5420_clock *clk =
samsung_get_base_clock(); (struct exynos5420_clock *)samsung_get_base_clock();
unsigned int *addr; void *addr;
unsigned int val; unsigned int val, shift;
/* addr = &clk->clk_div_fsys1;
* CLK_DIV_FSYS1 shift = dev_index * 10;
* MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
* CLK_DIV_FSYS2
* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
*/
if (dev_index < 2) {
addr = &clk->div_fsys1;
} else {
addr = &clk->div_fsys2;
dev_index -= 2;
}
val = readl(addr); val = readl(addr);
val &= ~(0xff << ((dev_index << 4) + 8)); val &= ~(0x3ff << shift);
val |= (div & 0xff) << ((dev_index << 4) + 8); val |= (div & 0x3ff) << shift;
writel(val, addr); writel(val, addr);
} }

457
src/cpu/samsung/exynos5420/clock_init.c
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@ -26,420 +26,175 @@
#include "dp.h" #include "dp.h"
#include "setup.h" #include "setup.h"
void system_clock_init(struct mem_timings *mem, void system_clock_init(void)
struct arm_clk_ratios *arm_clk_ratio)
{ {
struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; struct exynos5420_clock *clk =
(struct exynos5420_clock *)EXYNOS5_CLOCK_BASE;
struct exynos5_mct_regs *mct_regs = struct exynos5_mct_regs *mct_regs =
(struct exynos5_mct_regs *)EXYNOS5_MULTI_CORE_TIMER_BASE; (struct exynos5_mct_regs *)EXYNOS5_MULTI_CORE_TIMER_BASE;
u32 val, tmp; u32 val;
/* Turn on the MCT as early as possible. */ /* Turn on the MCT as early as possible. */
mct_regs->g_tcon |= (1 << 8); mct_regs->g_tcon |= (1 << 8);
clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
do {
val = readl(&clk->mux_stat_cpu);
} while ((val | MUX_APLL_SEL_MASK) != val);
clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
do {
val = readl(&clk->mux_stat_core1);
} while ((val | MUX_MPLL_SEL_MASK) != val);
clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
| MUX_GPLL_SEL_MASK;
do {
val = readl(&clk->mux_stat_top2);
} while ((val | tmp) != val);
clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
do {
val = readl(&clk->mux_stat_cdrex);
} while ((val | MUX_BPLL_SEL_MASK) != val);
/* PLL locktime */ /* PLL locktime */
writel(APLL_LOCK_VAL, &clk->apll_lock); writel(APLL_LOCK_VAL, &clk->apll_lock);
writel(MPLL_LOCK_VAL, &clk->mpll_lock); writel(MPLL_LOCK_VAL, &clk->mpll_lock);
writel(BPLL_LOCK_VAL, &clk->bpll_lock); writel(BPLL_LOCK_VAL, &clk->bpll_lock);
writel(CPLL_LOCK_VAL, &clk->cpll_lock); writel(CPLL_LOCK_VAL, &clk->cpll_lock);
writel(DPLL_LOCK_VAL, &clk->dpll_lock);
writel(GPLL_LOCK_VAL, &clk->gpll_lock);
writel(EPLL_LOCK_VAL, &clk->epll_lock); writel(EPLL_LOCK_VAL, &clk->epll_lock);
writel(VPLL_LOCK_VAL, &clk->vpll_lock); writel(VPLL_LOCK_VAL, &clk->vpll_lock);
writel(IPLL_LOCK_VAL, &clk->ipll_lock);
writel(SPLL_LOCK_VAL, &clk->spll_lock);
writel(KPLL_LOCK_VAL, &clk->kpll_lock);
writel(CLK_REG_DISABLE, &clk->pll_div2_sel); setbits_le32(&clk->clk_src_cpu, MUX_HPM_SEL_MASK);
writel(MUX_HPM_SEL_MASK, &clk->src_cpu); writel(0, &clk->clk_src_top6);
do {
val = readl(&clk->mux_stat_cpu);
} while ((val | HPM_SEL_SCLK_MPLL) != val);
val = arm_clk_ratio->arm2_ratio << 28 writel(0, &clk->clk_src_cdrex);
| arm_clk_ratio->apll_ratio << 24 writel(SRC_KFC_HPM_SEL, &clk->clk_src_kfc);
| arm_clk_ratio->pclk_dbg_ratio << 20 writel(HPM_RATIO, &clk->clk_div_cpu1);
| arm_clk_ratio->atb_ratio << 16 writel(CLK_DIV_CPU0_VAL, &clk->clk_div_cpu0);
| arm_clk_ratio->periph_ratio << 12
| arm_clk_ratio->acp_ratio << 8
| arm_clk_ratio->cpud_ratio << 4
| arm_clk_ratio->arm_ratio;
writel(val, &clk->div_cpu0);
do {
val = readl(&clk->div_stat_cpu0);
} while (0 != val);
writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
do {
val = readl(&clk->div_stat_cpu1);
} while (0 != val);
/* Set APLL */ /* Set APLL */
writel(APLL_CON1_VAL, &clk->apll_con1); writel(APLL_CON1_VAL, &clk->apll_con1);
val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, val = set_pll(0xc8, 0x3, 0x1);
arm_clk_ratio->apll_sdiv);
writel(val, &clk->apll_con0); writel(val, &clk->apll_con0);
while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0) while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
;
writel(SRC_KFC_HPM_SEL, &clk->clk_src_kfc);
writel(CLK_DIV_KFC_VAL, &clk->clk_div_kfc0);
/* Set KPLL*/
writel(KPLL_CON1_VAL, &clk->kpll_con1);
val = set_pll(0xc8, 0x2, 0x2);
writel(val, &clk->kpll_con0);
while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
; ;
/* Set MPLL */ /* Set MPLL */
writel(MPLL_CON1_VAL, &clk->mpll_con1); writel(MPLL_CON1_VAL, &clk->mpll_con1);
val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); val = set_pll(0xc8, 0x3, 0x1);
writel(val, &clk->mpll_con0); writel(val, &clk->mpll_con0);
while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0) while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
; ;
/* /* Set DPLL */
* Configure MUX_MPLL_FOUT to choose the direct clock source writel(DPLL_CON1_VAL, &clk->dpll_con1);
* path and avoid the fixed DIV/2 block to save power val = set_pll(0xc8, 0x2, 0x2);
*/ writel(val, &clk->dpll_con0);
setbits_le32(&clk->pll_div2_sel, MUX_MPLL_FOUT_SEL); while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
/* Set BPLL */
if (mem->use_bpll) {
writel(BPLL_CON1_VAL, &clk->bpll_con1);
val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
writel(val, &clk->bpll_con0);
while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
;
setbits_le32(&clk->pll_div2_sel, MUX_BPLL_FOUT_SEL);
}
/* Set CPLL */
writel(CPLL_CON1_VAL, &clk->cpll_con1);
val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
writel(val, &clk->cpll_con0);
while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
;
/* Set GPLL */
writel(GPLL_CON1_VAL, &clk->gpll_con1);
val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
writel(val, &clk->gpll_con0);
while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
; ;
/* Set EPLL */ /* Set EPLL */
writel(EPLL_CON2_VAL, &clk->epll_con2); writel(EPLL_CON2_VAL, &clk->epll_con2);
writel(EPLL_CON1_VAL, &clk->epll_con1); writel(EPLL_CON1_VAL, &clk->epll_con1);
val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); val = set_pll(0x64, 0x2, 0x1);
writel(val, &clk->epll_con0); writel(val, &clk->epll_con0);
while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0) while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
;
/* Set CPLL */
writel(CPLL_CON1_VAL, &clk->cpll_con1);
val = set_pll(0x6f, 0x2, 0x1);
writel(val, &clk->cpll_con0);
while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
;
/* Set IPLL */
writel(IPLL_CON1_VAL, &clk->ipll_con1);
val = set_pll(0xB9, 0x3, 0x2);
writel(val, &clk->ipll_con0);
while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
; ;
/* Set VPLL */ /* Set VPLL */
writel(VPLL_CON2_VAL, &clk->vpll_con2);
writel(VPLL_CON1_VAL, &clk->vpll_con1); writel(VPLL_CON1_VAL, &clk->vpll_con1);
val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); val = set_pll(0xd7, 0x3, 0x2);
writel(val, &clk->vpll_con0); writel(val, &clk->vpll_con0);
while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0) while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
; ;
writel(CLK_SRC_CORE0_VAL, &clk->src_core0); /* Set BPLL */
writel(CLK_DIV_CORE0_VAL, &clk->div_core0); writel(BPLL_CON1_VAL, &clk->bpll_con1);
while (readl(&clk->div_stat_core0) != 0) val = set_pll(0xc8, 0x3, 0x1);
writel(val, &clk->bpll_con0);
while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
; ;
writel(CLK_DIV_CORE1_VAL, &clk->div_core1); /* Set SPLL */
while (readl(&clk->div_stat_core1) != 0) writel(SPLL_CON1_VAL, &clk->spll_con1);
val = set_pll(0xc8, 0x2, 0x3);
writel(val, &clk->spll_con0);
while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
; ;
writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt); writel(CLK_DIV_CDREX0_VAL, &clk->clk_div_cdrex0);
while (readl(&clk->div_stat_sysrgt) != 0) writel(CLK_DIV_CDREX1_VAL, &clk->clk_div_cdrex1);
;
writel(CLK_DIV_ACP_VAL, &clk->div_acp); writel(CLK_SRC_TOP0_VAL, &clk->clk_src_top0);
while (readl(&clk->div_stat_acp) != 0) writel(CLK_SRC_TOP1_VAL, &clk->clk_src_top1);
; writel(CLK_SRC_TOP2_VAL, &clk->clk_src_top2);
writel(CLK_SRC_TOP7_VAL, &clk->clk_src_top7);
writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft); writel(CLK_DIV_TOP0_VAL, &clk->clk_div_top0);
while (readl(&clk->div_stat_syslft) != 0) writel(CLK_DIV_TOP1_VAL, &clk->clk_div_top1);
; writel(CLK_DIV_TOP2_VAL, &clk->clk_div_top2);
writel(CLK_SRC_TOP0_VAL, &clk->src_top0); writel(0, &clk->clk_src_top10);
writel(CLK_SRC_TOP1_VAL, &clk->src_top1); writel(0, &clk->clk_src_top11);
writel(TOP2_VAL, &clk->src_top2); writel(0, &clk->clk_src_top12);
writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
writel(CLK_DIV_TOP0_VAL, &clk->div_top0); writel(CLK_SRC_TOP3_VAL, &clk->clk_src_top3);
while (readl(&clk->div_stat_top0)) writel(CLK_SRC_TOP4_VAL, &clk->clk_src_top4);
; writel(CLK_SRC_TOP5_VAL, &clk->clk_src_top5);
writel(CLK_DIV_TOP1_VAL, &clk->div_top1); /* DISP1 BLK CLK SELECTION */
while (readl(&clk->div_stat_top1)) writel(CLK_SRC_DISP1_0_VAL, &clk->clk_src_disp10);
; writel(CLK_DIV_DISP1_0_VAL, &clk->clk_div_disp10);
writel(CLK_SRC_LEX_VAL, &clk->src_lex); /* AUDIO BLK */
while (1) { writel(AUDIO0_SEL_EPLL, &clk->clk_src_mau);
val = readl(&clk->mux_stat_lex); writel(DIV_MAU_VAL, &clk->clk_div_mau);
if (val == (val | 1))
break;
}
writel(CLK_DIV_LEX_VAL, &clk->div_lex); /* FSYS */
while (readl(&clk->div_stat_lex)) writel(CLK_SRC_FSYS0_VAL, &clk->clk_src_fsys);
; writel(CLK_DIV_FSYS0_VAL, &clk->clk_div_fsys0);
writel(CLK_DIV_FSYS1_VAL, &clk->clk_div_fsys1);
writel(CLK_DIV_FSYS2_VAL, &clk->clk_div_fsys2);
writel(CLK_DIV_R0X_VAL, &clk->div_r0x); writel(CLK_SRC_ISP_VAL, &clk->clk_src_isp);
while (readl(&clk->div_stat_r0x)) writel(CLK_DIV_ISP0_VAL, &clk->clk_div_isp0);
; writel(CLK_DIV_ISP1_VAL, &clk->clk_div_isp1);
writel(CLK_DIV_R0X_VAL, &clk->div_r0x); writel(CLK_SRC_PERIC0_VAL, &clk->clk_src_peric0);
while (readl(&clk->div_stat_r0x)) writel(CLK_SRC_PERIC1_VAL, &clk->clk_src_peric1);
;
writel(CLK_DIV_R1X_VAL, &clk->div_r1x); writel(CLK_DIV_PERIC0_VAL, &clk->clk_div_peric0);
while (readl(&clk->div_stat_r1x)) writel(CLK_DIV_PERIC1_VAL, &clk->clk_div_peric1);
; writel(CLK_DIV_PERIC2_VAL, &clk->clk_div_peric2);
writel(CLK_DIV_PERIC3_VAL, &clk->clk_div_peric3);
writel(CLK_DIV_PERIC4_VAL, &clk->clk_div_peric4);
if (mem->use_bpll) { writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
writel(MUX_BPLL_SEL_MASK | MUX_MCLK_CDREX_SEL | writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
MUX_MCLK_DPHY_SEL, &clk->src_cdrex); writel(CLK_DIV_G2D, &clk->clk_div_g2d);
} else {
writel(CLK_REG_DISABLE, &clk->src_cdrex);
}
writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex); writel(CLK_SRC_CPU_VAL, &clk->clk_src_cpu);
while (readl(&clk->div_stat_cdrex)) writel(CLK_SRC_TOP3_VAL, &clk->clk_src_top6);
; writel(CLK_SRC_CDREX_VAL, &clk->clk_src_cdrex);
writel(CLK_SRC_KFC_VAL, &clk->clk_src_kfc);
val = readl(&clk->src_cpu);
val |= CLK_SRC_CPU_VAL;
writel(val, &clk->src_cpu);
val = readl(&clk->src_top2);
val |= CLK_SRC_TOP2_VAL;
writel(val, &clk->src_top2);
val = readl(&clk->src_core1);
val |= CLK_SRC_CORE1_VAL;
writel(val, &clk->src_core1);
writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
while (readl(&clk->div_stat_fsys0))
;
writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
/* FIMD1 SRC CLK SELECTION */
writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
| MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
| MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
| MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
writel(val, &clk->div_fsys2);
} }
void clock_gate(void) void clock_gate(void)
{ {
struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; /* Not implemented for now. */
/* CLK_GATE_IP_SYSRGT */
clrbits_le32(&clk->gate_ip_sysrgt, CLK_C2C_MASK);
/* CLK_GATE_IP_ACP */
clrbits_le32(&clk->gate_ip_acp, CLK_SMMUG2D_MASK |
CLK_SMMUSSS_MASK |
CLK_SMMUMDMA_MASK |
CLK_ID_REMAPPER_MASK |
CLK_G2D_MASK |
CLK_SSS_MASK |
CLK_MDMA_MASK |
CLK_SECJTAG_MASK);
/* CLK_GATE_BUS_SYSLFT */
clrbits_le32(&clk->gate_bus_syslft, CLK_EFCLK_MASK);
/* CLK_GATE_IP_ISP0 */
clrbits_le32(&clk->gate_ip_isp0, CLK_UART_ISP_MASK |
CLK_WDT_ISP_MASK |
CLK_PWM_ISP_MASK |
CLK_MTCADC_ISP_MASK |
CLK_I2C1_ISP_MASK |
CLK_I2C0_ISP_MASK |
CLK_MPWM_ISP_MASK |
CLK_MCUCTL_ISP_MASK |
CLK_INT_COMB_ISP_MASK |
CLK_SMMU_MCUISP_MASK |
CLK_SMMU_SCALERP_MASK |
CLK_SMMU_SCALERC_MASK |
CLK_SMMU_FD_MASK |
CLK_SMMU_DRC_MASK |
CLK_SMMU_ISP_MASK |
CLK_GICISP_MASK |
CLK_ARM9S_MASK |
CLK_MCUISP_MASK |
CLK_SCALERP_MASK |
CLK_SCALERC_MASK |
CLK_FD_MASK |
CLK_DRC_MASK |
CLK_ISP_MASK);
/* CLK_GATE_IP_ISP1 */
clrbits_le32(&clk->gate_ip_isp1, CLK_SPI1_ISP_MASK |
CLK_SPI0_ISP_MASK |
CLK_SMMU3DNR_MASK |
CLK_SMMUDIS1_MASK |
CLK_SMMUDIS0_MASK |
CLK_SMMUODC_MASK |
CLK_3DNR_MASK |
CLK_DIS_MASK |
CLK_ODC_MASK);
/* CLK_GATE_SCLK_ISP */
clrbits_le32(&clk->gate_sclk_isp, SCLK_MPWM_ISP_MASK);
/* CLK_GATE_IP_GSCL */
clrbits_le32(&clk->gate_ip_gscl, CLK_SMMUFIMC_LITE2_MASK |
CLK_SMMUFIMC_LITE1_MASK |
CLK_SMMUFIMC_LITE0_MASK |
CLK_SMMUGSCL3_MASK |
CLK_SMMUGSCL2_MASK |
CLK_SMMUGSCL1_MASK |
CLK_SMMUGSCL0_MASK |
CLK_GSCL_WRAP_B_MASK |
CLK_GSCL_WRAP_A_MASK |
CLK_CAMIF_TOP_MASK |
CLK_GSCL3_MASK |
CLK_GSCL2_MASK |
CLK_GSCL1_MASK |
CLK_GSCL0_MASK);
/* CLK_GATE_IP_DISP1 */
clrbits_le32(&clk->gate_ip_disp1, CLK_SMMUTVX_MASK |
CLK_ASYNCTVX_MASK |
CLK_HDMI_MASK |
CLK_MIXER_MASK |
CLK_DSIM1_MASK);
/* CLK_GATE_IP_MFC */
clrbits_le32(&clk->gate_ip_mfc, CLK_SMMUMFCR_MASK |
CLK_SMMUMFCL_MASK |
CLK_MFC_MASK);
/* CLK_GATE_IP_GEN */
clrbits_le32(&clk->gate_ip_gen, CLK_SMMUMDMA1_MASK |
CLK_SMMUJPEG_MASK |
CLK_SMMUROTATOR_MASK |
CLK_MDMA1_MASK |
CLK_JPEG_MASK |
CLK_ROTATOR_MASK);
/* CLK_GATE_IP_FSYS */
clrbits_le32(&clk->gate_ip_fsys, CLK_WDT_IOP_MASK |
CLK_SMMUMCU_IOP_MASK |
CLK_SATA_PHY_I2C_MASK |
CLK_SATA_PHY_CTRL_MASK |
CLK_MCUCTL_MASK |
CLK_NFCON_MASK |
CLK_SMMURTIC_MASK |
CLK_RTIC_MASK |
CLK_MIPI_HSI_MASK |
CLK_USBOTG_MASK |
CLK_SATA_MASK |
CLK_PDMA1_MASK |
CLK_PDMA0_MASK |
CLK_MCU_IOP_MASK);
/* CLK_GATE_IP_PERIC */
clrbits_le32(&clk->gate_ip_peric, CLK_HS_I2C3_MASK |
CLK_HS_I2C2_MASK |
CLK_HS_I2C1_MASK |
CLK_HS_I2C0_MASK |
CLK_AC97_MASK |
CLK_SPDIF_MASK |
CLK_PCM2_MASK |
CLK_PCM1_MASK |
CLK_I2S2_MASK |
CLK_SPI2_MASK |
CLK_SPI0_MASK);
/*
* CLK_GATE_IP_PERIS
* Note: Keep CHIPID_APBIF ungated to ensure reading the product ID
* register (PRO_ID) works correctly when the OS kernel determines
* which chip it is running on.
*/
clrbits_le32(&clk->gate_ip_peris, CLK_RTC_MASK |
CLK_TZPC9_MASK |
CLK_TZPC8_MASK |
CLK_TZPC7_MASK |
CLK_TZPC6_MASK |
CLK_TZPC5_MASK |
CLK_TZPC4_MASK |
CLK_TZPC3_MASK |
CLK_TZPC2_MASK |
CLK_TZPC1_MASK |
CLK_TZPC0_MASK);
/* CLK_GATE_BLOCK */
clrbits_le32(&clk->gate_block, CLK_ACP_MASK);
/* CLK_GATE_IP_CDREX */
clrbits_le32(&clk->gate_ip_cdrex, CLK_DPHY0_MASK |
CLK_DPHY1_MASK |
CLK_TZASC_DRBXR_MASK);
} }
void clock_init_dp_clock(void) void clock_init_dp_clock(void)
{ {
struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; /* Not implemented for now. */
/* DP clock enable */
setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
/* We run DP at 267 Mhz */
setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
} }

373
src/cpu/samsung/exynos5420/setup.h
View File

@ -26,6 +26,8 @@ struct exynos5_dmc;
enum ddr_mode; enum ddr_mode;
struct exynos5_phy_control; struct exynos5_phy_control;
#define NOT_AVAILABLE 0
/* TZPC : Register Offsets */ /* TZPC : Register Offsets */
#define TZPC0_BASE 0x10100000 #define TZPC0_BASE 0x10100000
#define TZPC1_BASE 0x10110000 #define TZPC1_BASE 0x10110000
@ -39,34 +41,50 @@ struct exynos5_phy_control;
#define TZPC9_BASE 0x10190000 #define TZPC9_BASE 0x10190000
/* APLL_CON1 */ /* APLL_CON1 */
#define APLL_CON1_VAL (0x00203800) #define APLL_CON1_VAL (0x0020f300)
/* MPLL_CON1 */ /* MPLL_CON1 */
#define MPLL_CON1_VAL (0x00203800) #define MPLL_CON1_VAL (0x0020f300)
/* CPLL_CON1 */ /* CPLL_CON1 */
#define CPLL_CON1_VAL (0x00203800) #define CPLL_CON1_VAL (0x0020f300)
/* DPLL_CON1 */
#define DPLL_CON1_VAL (0x0020f300)
/* GPLL_CON1 */ /* GPLL_CON1 */
#define GPLL_CON1_VAL (0x00203800) #define GPLL_CON1_VAL (NOT_AVAILABLE)
/* EPLL_CON1, CON2 */ /* EPLL_CON1, CON2 */
#define EPLL_CON1_VAL 0x00000000 #define EPLL_CON1_VAL 0x00000000
#define EPLL_CON2_VAL 0x00000080 #define EPLL_CON2_VAL 0x00000080
/* VPLL_CON1, CON2 */ /* VPLL_CON1, CON2 */
#define VPLL_CON1_VAL 0x00000000 #define VPLL_CON1_VAL 0x0020f300
#define VPLL_CON2_VAL 0x00000080 #define VPLL_CON2_VAL NOT_AVAILABLE
/* RPLL_CON1, CON2 */
#define RPLL_CON1_VAL 0x00000000
#define RPLL_CON2_VAL 0x00000080
/* BPLL_CON1 */ /* BPLL_CON1 */
#define BPLL_CON1_VAL 0x00203800 #define BPLL_CON1_VAL 0x0020f300
/* SPLL_CON1 */
#define SPLL_CON1_VAL 0x0020f300
/* IPLL_CON1 */
#define IPLL_CON1_VAL 0x00000080
/* KPLL_CON1 */
#define KPLL_CON1_VAL 0x200000
/* Set PLL */ /* Set PLL */
#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
/* CLK_SRC_CPU */ /* CLK_SRC_CPU */
/* 0 = MOUTAPLL, 1 = SCLKMPLL */ /* 0 = MOUTAPLL, 1 = SCLKMPLL */
#define MUX_HPM_SEL 0 #define MUX_HPM_SEL 1
#define MUX_CPU_SEL 0 #define MUX_CPU_SEL 0
#define MUX_APLL_SEL 1 #define MUX_APLL_SEL 1
@ -146,20 +164,11 @@ struct exynos5_phy_control;
#define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16) #define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
#define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28) #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
/* CLK_DIV_CPU0_VAL */
#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \
| (APLL_RATIO << 24) \
| (PCLK_DBG_RATIO << 20) \
| (ATB_RATIO << 16) \
| (PERIPH_RATIO << 12) \
| (ACP_RATIO << 8) \
| (CPUD_RATIO << 4) \
| (ARM_RATIO))
/* CLK_FSYS */ /* CLK_FSYS */
#define CLK_SRC_FSYS0_VAL 0x66666 #define CLK_SRC_FSYS0_VAL 0x33033300
#define CLK_DIV_FSYS0_VAL 0x0BB00000 #define CLK_DIV_FSYS0_VAL 0x0
#define CLK_DIV_FSYS1_VAL 0x04f13c4f
#define CLK_DIV_FSYS2_VAL 0x041d0000
/* CLK_DIV_CPU1 */ /* CLK_DIV_CPU1 */
#define HPM_RATIO 0x2 #define HPM_RATIO 0x2
@ -191,141 +200,57 @@ struct exynos5_phy_control;
#define CLK_DIV_SYSLFT_VAL 0x00000311 #define CLK_DIV_SYSLFT_VAL 0x00000311
/* CLK_SRC_CDREX */ /* CLK_SRC_CDREX */
#define CLK_SRC_CDREX_VAL 0x1 #define CLK_SRC_CDREX_VAL 0x00000001
/* CLK_DIV_CDREX */ /* CLK_DIV_CDREX */
#define MCLK_CDREX2_RATIO 0x0 #define CLK_DIV_CDREX0_VAL 0x30010100
#define ACLK_EFCON_RATIO 0x1 #define CLK_DIV_CDREX1_VAL 0x300
#define MCLK_DPHY_RATIO 0x1
#define MCLK_CDREX_RATIO 0x1
#define ACLK_C2C_200_RATIO 0x1
#define C2C_CLK_400_RATIO 0x1
#define PCLK_CDREX_RATIO 0x1
#define ACLK_CDREX_RATIO 0x1
#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \ #define CLK_DIV_CDREX_VAL 0x17010100
| (C2C_CLK_400_RATIO << 6) \
| (PCLK_CDREX_RATIO << 4) \
| (ACLK_CDREX_RATIO))
/* CLK_SRC_TOP0 */ /* CLK_DIV_CPU0_VAL */
#define MUX_ACLK_300_GSCL_SEL 0x0 #define CLK_DIV_CPU0_VAL 0x01440020
#define MUX_ACLK_300_GSCL_MID_SEL 0x0
#define MUX_ACLK_400_G3D_MID_SEL 0x0
#define MUX_ACLK_333_SEL 0x0
#define MUX_ACLK_300_DISP1_SEL 0x0
#define MUX_ACLK_300_DISP1_MID_SEL 0x0
#define MUX_ACLK_200_SEL 0x0
#define MUX_ACLK_166_SEL 0x0
#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
| (MUX_ACLK_300_GSCL_MID_SEL << 24) \
| (MUX_ACLK_400_G3D_MID_SEL << 20) \
| (MUX_ACLK_333_SEL << 16) \
| (MUX_ACLK_300_DISP1_SEL << 15) \
| (MUX_ACLK_300_DISP1_MID_SEL << 14) \
| (MUX_ACLK_200_SEL << 12) \
| (MUX_ACLK_166_SEL << 8))
/* CLK_SRC_TOP1 */ /* CLK_SRC_TOP */
#define MUX_ACLK_400_G3D_SEL 0x1 #define CLK_SRC_TOP0_VAL 0x12221222
#define MUX_ACLK_400_ISP_SEL 0x0 #define CLK_SRC_TOP1_VAL 0x00100200
#define MUX_ACLK_400_IOP_SEL 0x0 #define CLK_SRC_TOP2_VAL 0x11101000
#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0 #define CLK_SRC_TOP3_VAL 0x11111111
#define MUX_ACLK_300_GSCL_MID1_SEL 0x0 #define CLK_SRC_TOP4_VAL 0x11110111
#define MUX_ACLK_300_DISP1_MID1_SEL 0x0 #define CLK_SRC_TOP5_VAL 0x11111100
#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ #define CLK_SRC_TOP7_VAL 0x00022200
|(MUX_ACLK_400_ISP_SEL << 24) \
|(MUX_ACLK_400_IOP_SEL << 20) \
|(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \
|(MUX_ACLK_300_GSCL_MID1_SEL << 12) \
|(MUX_ACLK_300_DISP1_MID1_SEL << 8))
/* CLK_SRC_TOP2 */ /* CLK_DIV_TOP */
#define MUX_GPLL_SEL 0x1 #define CLK_DIV_TOP0_VAL 0x23712311
#define MUX_BPLL_USER_SEL 0x0 #define CLK_DIV_TOP1_VAL 0x13100B00
#define MUX_MPLL_USER_SEL 0x0 #define CLK_DIV_TOP2_VAL 0x11101100
#define MUX_VPLL_SEL 0x1
#define MUX_EPLL_SEL 0x1
#define MUX_CPLL_SEL 0x1
#define VPLLSRC_SEL 0x0
#define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \
| (MUX_BPLL_USER_SEL << 24) \
| (MUX_MPLL_USER_SEL << 20) \
| (MUX_VPLL_SEL << 16) \
| (MUX_EPLL_SEL << 12) \
| (MUX_CPLL_SEL << 8) \
| (VPLLSRC_SEL))
/* CLK_SRC_TOP3 */
#define MUX_ACLK_333_SUB_SEL 0x1
#define MUX_ACLK_400_SUB_SEL 0x1
#define MUX_ACLK_266_ISP_SUB_SEL 0x1
#define MUX_ACLK_266_GPS_SUB_SEL 0x0
#define MUX_ACLK_300_GSCL_SUB_SEL 0x1
#define MUX_ACLK_266_GSCL_SUB_SEL 0x1
#define MUX_ACLK_300_DISP1_SUB_SEL 0x1
#define MUX_ACLK_200_DISP1_SUB_SEL 0x1
#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
| (MUX_ACLK_400_SUB_SEL << 20) \
| (MUX_ACLK_266_ISP_SUB_SEL << 16) \
| (MUX_ACLK_266_GPS_SUB_SEL << 12) \
| (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
| (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
| (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
| (MUX_ACLK_200_DISP1_SUB_SEL << 4))
/* CLK_DIV_TOP0 */
#define ACLK_300_DISP1_RATIO 0x2
#define ACLK_400_G3D_RATIO 0x0
#define ACLK_333_RATIO 0x0
#define ACLK_266_RATIO 0x2
#define ACLK_200_RATIO 0x3
#define ACLK_166_RATIO 0x1
#define ACLK_133_RATIO 0x1
#define ACLK_66_RATIO 0x5
#define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \
| (ACLK_400_G3D_RATIO << 24) \
| (ACLK_333_RATIO << 20) \
| (ACLK_266_RATIO << 16) \
| (ACLK_200_RATIO << 12) \
| (ACLK_166_RATIO << 8) \
| (ACLK_133_RATIO << 4) \
| (ACLK_66_RATIO))
/* CLK_DIV_TOP1 */
#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
#define ACLK_66_PRE_RATIO 0x1
#define ACLK_400_ISP_RATIO 0x1
#define ACLK_400_IOP_RATIO 0x1
#define ACLK_300_GSCL_RATIO 0x2
#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
| (ACLK_66_PRE_RATIO << 24) \
| (ACLK_400_ISP_RATIO << 20) \
| (ACLK_400_IOP_RATIO << 16) \
| (ACLK_300_GSCL_RATIO << 12))
/* APLL_LOCK */ /* APLL_LOCK */
#define APLL_LOCK_VAL (0x546) #define APLL_LOCK_VAL (0x320)
/* MPLL_LOCK */ /* MPLL_LOCK */
#define MPLL_LOCK_VAL (0x546) #define MPLL_LOCK_VAL (0x258)
/* CPLL_LOCK */
#define CPLL_LOCK_VAL (0x546)
/* GPLL_LOCK */
#define GPLL_LOCK_VAL (0x546)
/* EPLL_LOCK */
#define EPLL_LOCK_VAL (0x3A98)
/* VPLL_LOCK */
#define VPLL_LOCK_VAL (0x3A98)
/* BPLL_LOCK */ /* BPLL_LOCK */
#define BPLL_LOCK_VAL (0x546) #define BPLL_LOCK_VAL (0x258)
/* CPLL_LOCK */
#define MUX_MCLK_CDREX_SEL (1 << 4) #define CPLL_LOCK_VAL (0x190)
#define MUX_MCLK_DPHY_SEL (1 << 8) /* DPLL_LOCK */
#define DPLL_LOCK_VAL (0x190)
/* GPLL_LOCK */
#define GPLL_LOCK_VAL NOT_AVAILABLE
/* IPLL_LOCK */
#define IPLL_LOCK_VAL (0x320)
/* KPLL_LOCK */
#define KPLL_LOCK_VAL (0x258)
/* SPLL_LOCK */
#define SPLL_LOCK_VAL (0x320)
/* RPLL_LOCK */
#define RPLL_LOCK_VAL (0x2328)
/* EPLL_LOCK */
#define EPLL_LOCK_VAL (0x2328)
/* VPLL_LOCK */
#define VPLL_LOCK_VAL (0x258)
#define MUX_APLL_SEL_MASK (1 << 0) #define MUX_APLL_SEL_MASK (1 << 0)
#define MUX_MPLL_FOUT_SEL (1 << 4)
#define MUX_BPLL_FOUT_SEL (1 << 0)
#define MUX_MPLL_SEL_MASK (1 << 8) #define MUX_MPLL_SEL_MASK (1 << 8)
#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8) #define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
#define MUX_CPLL_SEL_MASK (1 << 8) #define MUX_CPLL_SEL_MASK (1 << 8)
@ -335,6 +260,7 @@ struct exynos5_phy_control;
#define MUX_BPLL_SEL_MASK (1 << 0) #define MUX_BPLL_SEL_MASK (1 << 0)
#define MUX_HPM_SEL_MASK (1 << 20) #define MUX_HPM_SEL_MASK (1 << 20)
#define HPM_SEL_SCLK_MPLL (1 << 21) #define HPM_SEL_SCLK_MPLL (1 << 21)
#define PLL_LOCKED (1 << 29)
#define APLL_CON0_LOCKED (1 << 29) #define APLL_CON0_LOCKED (1 << 29)
#define MPLL_CON0_LOCKED (1 << 29) #define MPLL_CON0_LOCKED (1 << 29)
#define BPLL_CON0_LOCKED (1 << 29) #define BPLL_CON0_LOCKED (1 << 29)
@ -345,33 +271,75 @@ struct exynos5_phy_control;
#define CLK_REG_DISABLE 0x0 #define CLK_REG_DISABLE 0x0
#define TOP2_VAL 0x0110000 #define TOP2_VAL 0x0110000
/* CLK_SRC_LEX */
#define CLK_SRC_LEX_VAL 0x0
/* CLK_DIV_LEX */
#define CLK_DIV_LEX_VAL 0x10
/* CLK_DIV_R0X */
#define CLK_DIV_R0X_VAL 0x10
/* CLK_DIV_L0X */
#define CLK_DIV_R1X_VAL 0x10
/* CLK_DIV_ISP2 */
#define CLK_DIV_ISP2_VAL 0x1
/* CLK_SRC_KFC */
#define SRC_KFC_HPM_SEL (1 << 15)
/* CLK_SRC_KFC */
#define CLK_SRC_KFC_VAL 0x00008001
/* CLK_DIV_KFC */
#define CLK_DIV_KFC_VAL 0x03300110
/* CLK_DIV2_RATIO */
#define CLK_DIV2_RATIO 0x10111150
/* CLK_DIV4_RATIO */
#define CLK_DIV4_RATIO 0x00000003
/* CLK_DIV_G2D */
#define CLK_DIV_G2D 0x00000010
/* CLK_SRC_PERIC0 */ /* CLK_SRC_PERIC0 */
#define PWM_SEL 6 #define SPDIF_SEL 1
#define UART3_SEL 6 #define PWM_SEL 3
#define UART2_SEL 6 #define UART4_SEL 3
#define UART1_SEL 6 #define UART3_SEL 3
#define UART0_SEL 6 #define UART2_SEL 3
/* SRC_CLOCK = SCLK_MPLL */ #define UART1_SEL 3
#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \ #define UART0_SEL 3
| (UART3_SEL << 12) \ /* SRC_CLOCK = SCLK_RPLL */
| (UART2_SEL << 8) \ #define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \
| (UART1_SEL << 4) \ | (PWM_SEL << 24) \
| (UART0_SEL)) | (UART4_SEL << 20) \
| (UART3_SEL << 16) \
| (UART2_SEL << 12) \
| (UART1_SEL << 8) \
| (UART0_SEL << 4))
/* CLK_SRC_PERIC1 */ /* CLK_SRC_PERIC1 */
/* SRC_CLOCK = SCLK_MPLL */ /* SRC_CLOCK = SCLK_EPLL */
#define SPI0_SEL 6 #define SPI0_SEL 6
#define SPI1_SEL 6 #define SPI1_SEL 6
#define SPI2_SEL 6 #define SPI2_SEL 6
#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \ #define AUDIO0_SEL 6
| (SPI1_SEL << 20) \ #define AUDIO1_SEL 6
| (SPI0_SEL << 16)) #define AUDIO2_SEL 6
#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \
| (SPI1_SEL << 24) \
| (SPI0_SEL << 20) \
| (AUDIO2_SEL << 16) \
| (AUDIO2_SEL << 12) \
| (AUDIO2_SEL << 8))
/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */ /* CLK_SRC_ISP */
#define SPI0_ISP_SEL 6 #define CLK_SRC_ISP_VAL 0x33366000
#define SPI1_ISP_SEL 6 #define CLK_DIV_ISP0_VAL 0x13131300
#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \ #define CLK_DIV_ISP1_VAL 0xbb110202
| (SPI0_ISP_SEL << 0)
/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */ /* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
#define SPI0_ISP_RATIO 0xf #define SPI0_ISP_RATIO 0xf
@ -380,32 +348,50 @@ struct exynos5_phy_control;
| (SPI0_ISP_RATIO << 0) | (SPI0_ISP_RATIO << 0)
/* CLK_DIV_PERIL0 */ /* CLK_DIV_PERIL0 */
#define UART5_RATIO 7 #define PWM_RATIO 8
#define UART4_RATIO 7 #define UART4_RATIO 9
#define UART3_RATIO 7 #define UART3_RATIO 9
#define UART2_RATIO 7 #define UART2_RATIO 9
#define UART1_RATIO 7 #define UART1_RATIO 9
#define UART0_RATIO 7 #define UART0_RATIO 9
#define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \
| (UART4_RATIO << 24) \
| (UART3_RATIO << 20) \
| (UART2_RATIO << 16) \
| (UART1_RATIO << 12) \
| (UART0_RATIO << 8))
#define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \
| (UART2_RATIO << 8) \
| (UART1_RATIO << 4) \
| (UART0_RATIO))
/* CLK_DIV_PERIC1 */ /* CLK_DIV_PERIC1 */
#define SPI1_RATIO 0x7 #define SPI2_RATIO 0x1
#define SPI0_RATIO 0xf #define SPI1_RATIO 0x1
#define SPI1_SUB_RATIO 0x0 #define SPI0_RATIO 0x1
#define SPI0_SUB_RATIO 0x0 #define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \
#define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \ | (SPI1_RATIO << 24) \
| ((SPI1_RATIO << 16) \ | (SPI0_RATIO << 20))
| (SPI0_SUB_RATIO << 8) \
| (SPI0_RATIO << 0)))
/* CLK_DIV_PERIC2 */ /* CLK_DIV_PERIC2 */
#define SPI2_RATIO 0xf #define PCM2_RATIO 0x3
#define SPI2_SUB_RATIO 0x0 #define PCM1_RATIO 0x3
#define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \ #define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \
| (SPI2_RATIO << 0)) | (PCM1_RATIO << 16))
/* CLK_DIV_PERIC3 */
#define AUDIO2_RATIO 0x5
#define AUDIO1_RATIO 0x5
#define AUDIO0_RATIO 0x5
#define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \
| (AUDIO1_RATIO << 24) \
| (AUDIO0_RATIO << 20))
/* CLK_DIV_PERIC4 */
#define SPI2_PRE_RATIO 0x2
#define SPI1_PRE_RATIO 0x2
#define SPI0_PRE_RATIO 0x2
#define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \
| (SPI1_PRE_RATIO << 16) \
| (SPI0_PRE_RATIO << 8))
/* CLK_DIV_FSYS2 */ /* CLK_DIV_FSYS2 */
#define MMC2_RATIO_MASK 0xf #define MMC2_RATIO_MASK 0xf
#define MMC2_RATIO_VAL 0x3 #define MMC2_RATIO_VAL 0x3
@ -435,17 +421,12 @@ struct exynos5_phy_control;
/* CLK_DIV_L0X */ /* CLK_DIV_L0X */
#define CLK_DIV_R1X_VAL 0x10 #define CLK_DIV_R1X_VAL 0x10
/* CLK_DIV_ISP0 */
#define CLK_DIV_ISP0_VAL 0x31
/* CLK_DIV_ISP1 */
#define CLK_DIV_ISP1_VAL 0x0
/* CLK_DIV_ISP2 */ /* CLK_DIV_ISP2 */
#define CLK_DIV_ISP2_VAL 0x1 #define CLK_DIV_ISP2_VAL 0x1
/* CLK_SRC_DISP1_0 */ /* CLK_SRC_DISP1_0 */
#define CLK_SRC_DISP1_0_VAL 0x6 #define CLK_SRC_DISP1_0_VAL 0x10666600
#define CLK_DIV_DISP1_0_VAL 0x01050210
/* /*
* DIV_DISP1_0 * DIV_DISP1_0
@ -538,6 +519,12 @@ struct exynos5_phy_control;
#define CLK_MIXER_MASK (1 << 5) #define CLK_MIXER_MASK (1 << 5)
#define CLK_DSIM1_MASK (1 << 3) #define CLK_DSIM1_MASK (1 << 3)
/* AUDIO CLK SEL */
#define AUDIO0_SEL_EPLL (0x6 << 28)
#define AUDIO0_RATIO 0x5
#define PCM0_RATIO 0x3
#define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20)
/* CLK_GATE_IP_GEN */ /* CLK_GATE_IP_GEN */
#define CLK_SMMUMDMA1_MASK (1 << 9) #define CLK_SMMUMDMA1_MASK (1 << 9)
#define CLK_SMMUJPEG_MASK (1 << 7) #define CLK_SMMUJPEG_MASK (1 << 7)

5
src/mainboard/google/pit/romstage.c
View File

@ -150,11 +150,12 @@ static void setup_memory(struct mem_timings *mem, int is_resume)
static struct mem_timings *setup_clock(void) static struct mem_timings *setup_clock(void)
{ {
struct mem_timings *mem = get_mem_timings(); struct mem_timings *mem = get_mem_timings();
struct arm_clk_ratios *arm_ratios = get_arm_clk_ratios();
if (!mem) { if (!mem) {
die("Unable to auto-detect memory timings\n"); die("Unable to auto-detect memory timings\n");
} }
system_clock_init(mem, arm_ratios);
system_clock_init();
return mem; return mem;
} }