Update Kontron board
- use new features of the ich7 update - move rambase above 1M to avoid memory trashing through SMM relocation - enable superio HWM Update ICH7 driver - minor smi cosmetics (in progress) - add real ac97 driver - add real azalia driver - fix some interrupt issues - fix some sata issues - include Patrick's fix for _lpc.c Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
977ed2d995
commit
54309d637a
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@ -82,7 +82,7 @@ if HAVE_ACPI_TABLES
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object acpi_tables.o
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makerule dsdt.c
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depends "$(MAINBOARD)/dsdt.dsl"
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action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.dsl"
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action "iasl -p dsdt -tc $(MAINBOARD)/dsdt.dsl"
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action "mv $(PWD)/dsdt.hex dsdt.c"
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end
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object ./dsdt.o
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@ -187,9 +187,18 @@ chip northbridge/intel/i945
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device pci 02.1 on end # display controller
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chip southbridge/intel/i82801gx
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register "pirqa_routing" = "0x05"
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register "pirqb_routing" = "0x07"
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register "pirqc_routing" = "0x06"
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register "pirqd_routing" = "0x07"
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register "pirqe_routing" = "0x80"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x05"
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register "ide_legacy_combined" = "0x1"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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register "sata_ahci" = "0x0"
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device pci 1b.0 on end # High Definition Audio
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@ -233,7 +233,7 @@ default FALLBACK_SIZE=131072
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##
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## coreboot C code runs at this location in RAM
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##
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default _RAMBASE=0x00004000
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default _RAMBASE=0x00100000
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##
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## Load the payload from the ROM
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@ -169,6 +169,13 @@ static void early_superio_config_w83627thg(void)
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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/* Enable HWM */
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dev=PNP_DEV(0x2e, W83627THG_HWM);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
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pnp_set_enable(dev, 1);
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pnp_exit_ext_func_mode(dev);
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dev=PNP_DEV(0x4e, W83627THG_SP1);
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@ -1,7 +1,7 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 coresystems GmbH
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## Copyright (C) 2008-2009 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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@ -23,6 +23,7 @@ uses HAVE_SMI_HANDLER
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config chip.h
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driver i82801gx.o
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driver i82801gx_ac97.o
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driver i82801gx_azalia.o
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driver i82801gx_ide.o
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driver i82801gx_lpc.o
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driver i82801gx_nic.o
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 coresystems GmbH
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -22,10 +22,24 @@
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#define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
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struct southbridge_intel_i82801gx_config {
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/* LPC configuration */
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uint8_t pirqa_routing;
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uint8_t pirqb_routing;
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uint8_t pirqc_routing;
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uint8_t pirqd_routing;
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uint8_t pirqe_routing;
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uint8_t pirqf_routing;
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uint8_t pirqg_routing;
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uint8_t pirqh_routing;
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/* IDE configuration */
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uint32_t ide_legacy_combined;
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uint32_t ide_enable_primary;
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uint32_t ide_enable_secondary;
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uint32_t sata_ahci;
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/* Azalia Configuration */
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unsigned long hda_viddid;
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};
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extern struct chip_operations southbridge_intel_i82801gx_ops;
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 coresystems GmbH
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -22,16 +22,234 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include <delay.h>
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#include "i82801gx.h"
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#define NAMBAR 0x10
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#define MASTER_VOL 0x02
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#define PAGING 0x24
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#define EXT_AUDIO 0x28
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#define FUNC_SEL 0x66
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#define INFO_IO 0x68
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#define CONNECTOR 0x6a
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#define VENDOR_ID1 0x7c
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#define VENDOR_ID2 0x7e
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#define SEC_VENDOR_ID1 0xfc
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#define SEC_VENDOR_ID2 0xfe
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#define NABMBAR 0x14
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#define GLOB_CNT 0x2c
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#define GLOB_STA 0x30
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#define CAS 0x34
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#define MMBAR 0x10
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#define EXT_MODEM_ID1 0x3c
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#define EXT_MODEM_ID2 0xbc
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#define MBAR 0x14
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#define SEC_CODEC 0x40
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/* FIXME. This table is probably mainboard specific */
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static u16 ac97_function[16*2][4] = {
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) }
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};
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static u16 nabmbar;
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static u16 nambar;
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static int ac97_semaphore(void)
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{
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int timeout;
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u8 reg8;
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timeout = 0xffff;
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do {
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reg8 = inb(nabmbar + CAS);
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timeout--;
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} while ((reg8 & 1) && timeout);
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if (! timeout) {
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printk_debug("Timeout!\n");
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}
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return (!timeout);
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}
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static void init_cnr(void)
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{
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// TODO
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}
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static void program_sigid(struct device *dev, u32 id)
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{
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pci_write_config32(dev, 0x2c, id);
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}
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static void ac97_audio_init(struct device *dev)
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{
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// XXX init AC97 codecs.
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u8 reg8;
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u16 reg16;
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u32 reg32;
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int i;
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printk_debug("Initializing AC'97 Audio.\n");
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/* top 16 bits are zero, so don't read them */
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nabmbar = pci_read_config16(dev, NABMBAR) & 0xfffe;
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nambar = pci_read_config16(dev, NAMBAR) & 0xfffe;
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reg16 = inw(nabmbar + GLOB_CNT);
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reg16 |= (1 << 1); /* Remove AC_RESET# */
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outw(reg16, nabmbar + GLOB_CNT);
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/* Wait 600ms. Ouch. */
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udelay(600 * 1000);
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init_cnr();
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/* Detect Primary AC'97 Codec */
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reg32 = inl(nabmbar + GLOB_STA);
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if ((reg32 & ((1 << 28) | (1 << 9) | (1 << 8))) == 0) {
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/* Primary Codec not found */
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printk_debug("No primary codec. Disabling AC'97 Audio.\n");
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return;
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}
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ac97_semaphore();
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/* Detect if codec is programmable */
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outw(0x8000, nambar + MASTER_VOL);
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ac97_semaphore();
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if (inw(nambar + MASTER_VOL) != 0x8000) {
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printk_debug("Codec not programmable. Disabling AC'97 Audio.\n");
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return;
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}
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/* Program Vendor IDs */
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reg32 = inw(nambar + VENDOR_ID1);
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reg32 <<= 16;
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reg32 |= (u16)inw(nambar + VENDOR_ID2);
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program_sigid(dev, reg32);
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/* Is Codec AC'97 2.3 compliant? */
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reg16 = inw(nambar + EXT_AUDIO);
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/* [11:10] = 10b -> AC'97 2.3 */
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if ((reg16 & 0x0c00) != 0x0800) {
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/* No 2.3 Codec. We're done */
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return;
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}
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/* Select Page 1 */
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reg16 = inw(nambar + PAGING);
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reg16 &= 0xfff0;
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reg16 |= 0x0001;
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outw(reg16, nambar + PAGING);
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for (i = 0x0a * 2; i > 0; i--) {
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outw(i, nambar + FUNC_SEL);
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/* Function could not be selected. Next one */
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if (inw(nambar + FUNC_SEL) != i)
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continue;
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reg16 = inw(nambar + INFO_IO);
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/* Function Information present? */
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if (!(reg16 & (1 << 0)))
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continue;
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/* Function Information valid? */
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if (!(reg16 & (1 << 4)))
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continue;
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/* Program Buffer Delay [9:5] */
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reg16 &= 0x03e0;
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reg16 |= ac97_function[i][0];
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/* Program Gain [15:11] */
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reg16 |= ac97_function[i][1];
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/* Program Inversion [10] */
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reg16 |= ac97_function[i][2];
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outw(reg16, nambar + INFO_IO);
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/* Program Connector / Jack Location */
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reg16 = inw(nambar + CONNECTOR);
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reg16 &= 0x1fff;
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reg16 |= ac97_function[i][3];
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outw(reg16, nambar + CONNECTOR);
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}
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}
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static void ac97_modem_init(struct device *dev)
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{
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// XXX init modem?
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u16 reg16;
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u32 reg32;
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u16 mmbar, mbar;
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mmbar = pci_read_config16(dev, MMBAR) & 0xfffe;
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mbar = pci_read_config16(dev, MBAR) & 0xfffe;
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reg16 = inw(mmbar + EXT_MODEM_ID1);
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if ((reg16 & 0xc000) != 0xc000 ) {
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if (reg16 & (1 << 0)) {
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reg32 = inw(mmbar + VENDOR_ID2);
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reg32 <<= 16;
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reg32 |= (u16)inw(mmbar + VENDOR_ID1);
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program_sigid(dev, reg32);
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return;
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}
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}
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/* Secondary codec? */
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reg16 = inw(mbar + SEC_CODEC);
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if ((reg16 & (1 << 9)) == 0)
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return;
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reg16 = inw(mmbar + EXT_MODEM_ID2);
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if ((reg16 & 0xc000) == 0x4000) {
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if (reg16 & (1 << 0)) {
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reg32 = inw(mmbar + SEC_VENDOR_ID2);
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reg32 <<= 16;
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reg32 |= (u16)inw(mmbar + SEC_VENDOR_ID1);
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program_sigid(dev, reg32);
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return;
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}
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}
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}
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static struct device_operations ac97_audio_ops = {
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 coresystems GmbH
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -24,6 +24,7 @@
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#include <device/pci_ids.h>
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#include <pc80/mc146818rtc.h>
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#include <pc80/isa-dma.h>
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#include <pc80/i8259.h>
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#include <arch/io.h>
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#include "i82801gx.h"
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@ -38,6 +39,8 @@
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#define NMI_OFF 0
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typedef struct southbridge_intel_i82801gx_config config_t;
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/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
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* 0x00 - 0000 = Reserved
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* 0x01 - 0001 = Reserved
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@ -108,15 +111,44 @@ static void i82801gx_enable_serial_irqs(struct device *dev)
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static void i82801gx_pirq_init(device_t dev)
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{
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pci_write_config8(dev, PIRQA_ROUT, 0x85);
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pci_write_config8(dev, PIRQB_ROUT, 0x87);
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pci_write_config8(dev, PIRQC_ROUT, 0x86);
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pci_write_config8(dev, PIRQD_ROUT, 0x87);
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device_t irq_dev;
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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pci_write_config8(dev, PIRQE_ROUT, 0x80);
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pci_write_config8(dev, PIRQF_ROUT, 0x80);
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pci_write_config8(dev, PIRQG_ROUT, 0x80);
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pci_write_config8(dev, PIRQH_ROUT, 0x85);
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pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
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pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
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pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
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pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
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pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
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pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
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pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
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pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
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/* Eric Biederman once said we should let the OS do this.
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* I am not so sure anymore he was right.
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*/
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for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
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u8 int_pin=0, int_line=0;
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if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
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continue;
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int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
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switch (int_pin) {
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case 1: /* INTA# */ int_line = config->pirqa_routing; break;
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case 2: /* INTB# */ int_line = config->pirqb_routing; break;
|
||||
case 3: /* INTC# */ int_line = config->pirqc_routing; break;
|
||||
case 4: /* INTD# */ int_line = config->pirqd_routing; break;
|
||||
}
|
||||
|
||||
if (!int_line)
|
||||
continue;
|
||||
|
||||
pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
|
||||
}
|
||||
}
|
||||
|
||||
static void i82801gx_power_options(device_t dev)
|
||||
|
|
@ -328,8 +360,8 @@ static struct device_operations device_ops = {
|
|||
.ops_pci = &pci_ops,
|
||||
};
|
||||
|
||||
/* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
|
||||
static const struct pci_driver ich7_ich7r_ich7dh_lpc __pci_driver = {
|
||||
/* 82801GB/GR (ICH7/ICH7R) */
|
||||
static const struct pci_driver ich7_ich7r_lpc __pci_driver = {
|
||||
.ops = &device_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x27b8,
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 coresystems GmbH
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -46,6 +46,9 @@ static void pci_init(struct device *dev)
|
|||
reg16 = pci_read_config16(dev, 0x1e);
|
||||
reg16 |= 0xf900;
|
||||
pci_write_config16(dev, 0x1e, reg16);
|
||||
|
||||
/* Will this improve throughput of bus masters? */
|
||||
pci_write_config8(dev, PCI_MIN_GNT, 0x06);
|
||||
}
|
||||
|
||||
static void ich_pci_dev_enable_resources(struct device *dev)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 coresystems GmbH
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -53,13 +53,13 @@ static void pci_init(struct device *dev)
|
|||
pci_write_config16(dev, 0x1e, reg16);
|
||||
|
||||
reg32 = pci_read_config32(dev, 0x20);
|
||||
printk_debug(" MBL = 0x%08x\n", reg32);
|
||||
printk_spew(" MBL = 0x%08x\n", reg32);
|
||||
reg32 = pci_read_config32(dev, 0x24);
|
||||
printk_debug(" PMBL = 0x%08x\n", reg32);
|
||||
printk_spew(" PMBL = 0x%08x\n", reg32);
|
||||
reg32 = pci_read_config32(dev, 0x28);
|
||||
printk_debug(" PMBU32 = 0x%08x\n", reg32);
|
||||
printk_spew(" PMBU32 = 0x%08x\n", reg32);
|
||||
reg32 = pci_read_config32(dev, 0x2c);
|
||||
printk_debug(" PMLU32 = 0x%08x\n", reg32);
|
||||
printk_spew(" PMLU32 = 0x%08x\n", reg32);
|
||||
}
|
||||
|
||||
static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 coresystems GmbH
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -133,6 +133,8 @@ static void sata_init(struct device *dev)
|
|||
reg32 |= 0x121200aa;
|
||||
pci_write_config32(dev, 0xa4, reg32);
|
||||
pci_write_config8(dev, 0xa0, 0x00);
|
||||
|
||||
pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
|
||||
}
|
||||
|
||||
static struct device_operations sata_ops = {
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 coresystems GmbH
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
|
|
@ -248,16 +248,26 @@ void southbridge_io_trap_handler(int smif)
|
|||
|
||||
printk_debug("SMI function trap 0x%x: ", smif);
|
||||
|
||||
|
||||
switch (smif) {
|
||||
case 0x32:
|
||||
printk_debug("OS Init\n");
|
||||
//gnvs->smif = 0;
|
||||
break;
|
||||
case 0xd5:
|
||||
printk_debug("Set Brightness\n");
|
||||
reg8 = gnvs->brtl;
|
||||
printk_debug("brtl: %x\n", reg8);
|
||||
outb(0x17, 0x66);
|
||||
outb(reg8, 0x62);
|
||||
//gnvs->smif = 0;
|
||||
break;
|
||||
case 0xd6:
|
||||
printk_debug("Get Brightness\n");
|
||||
outb(0x17, 0x66);
|
||||
reg8 = inb(0x62);
|
||||
printk_debug("brtl: %x\n", reg8);
|
||||
gnvs->brtl = reg8;
|
||||
//gnvs->smif = 0;
|
||||
break;
|
||||
default:
|
||||
printk_debug("Unknown function\n");
|
||||
|
|
@ -401,12 +411,24 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
|
|||
|
||||
if (smi_sts & (1 << 4)) { // SLP_SMI
|
||||
u32 reg32;
|
||||
|
||||
/* First, disable further SMIs */
|
||||
reg8 = inb(pmbase + SMI_EN);
|
||||
reg8 &= ~SLP_SMI_EN;
|
||||
outb(reg8, pmbase + SMI_EN);
|
||||
|
||||
/* Next, do the deed, we should change
|
||||
* power on after power loss bits here
|
||||
* if we're going to S5
|
||||
*/
|
||||
|
||||
/* Write back to the SLP register to cause the
|
||||
* originally intended event again.
|
||||
*/
|
||||
reg32 = inl(pmbase + 0x04);
|
||||
printk_debug("SMI#: SLP = 0x%08x\n");
|
||||
printk_debug("SMI#: Powering off.\n");
|
||||
outl((6 << 10), pmbase + 0x04);
|
||||
outl((1 << 13) | (6 << 10), pmbase + 0x04);
|
||||
printk_debug("....\n");
|
||||
outl(reg32, pmbase + 0x04);
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue