From 5434deaf2a32e12c8b640fc80486b72d13408c01 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 18 May 2020 12:35:18 -0700 Subject: [PATCH] soc/intel/common/block/acpi: Fix error in shift operation for GPCL CB:41454 updated northbridge.asl to ASL2.0 syntax. During this, GPCL was incorrectly updated to use << (ShiftLeft) instead of >> (ShiftRight). This change fixes the error in GPCL by updating it to use >> (ShiftRight). TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for hatch. Change-Id: I36469cb3b0bcc595acf0e43808d6a574986cad68 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41519 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/acpi/acpi/northbridge.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 53b21881ae..bac059076a 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -229,7 +229,7 @@ Method (GPCB, 0, Serialized) /* Get PCIe Length */ Method (GPCL, 0, Serialized) { - Local0 = 0x10000000 << \_SB.PCI0.MCHC.PXSZ + Local0 = 0x10000000 >> \_SB.PCI0.MCHC.PXSZ Return (Local0) }