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soc/mediatek/mt8195: fine tune pmif spi hardware settings for stability 

Update IO driving setting for pmif spi.

Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com>
Change-Id: I48268cda8845a591592d8ca828ffe492e6dfe0ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56166
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
James Lo 2021-07-03 13:54:45 +08:00 committed by Hung-Te Lin
parent e46cd138ff
commit 543b32f60d
2 changed files with 4 additions and 3 deletions
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1
src/soc/mediatek/mt8195/include/soc/iocfg.h
View File

@ -63,5 +63,6 @@ check_member(mt8195_iocfg_bm_regs, tdsel_cfg1, 0x110);
enum { enum {
IO_4_MA = 0x9, IO_4_MA = 0x9,
IO_6_MA = 0x1b,
}; };
#endif /* __SOC_MEDIATEK_MT8195_IOCFG_H__ */ #endif /* __SOC_MEDIATEK_MT8195_IOCFG_H__ */

6
src/soc/mediatek/mt8195/pmif_spi.c
View File

@ -10,7 +10,7 @@ DEFINE_BITFIELD(PWRAP_SPI1_DRIVING, 5, 0)
void pmif_spi_iocfg(void) void pmif_spi_iocfg(void)
{ {
/* Set SoC SPI IO driving strength to 4 mA */ /* Set SoC SPI IO driving strength to 6 mA */
SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg1, PWRAP_SPI0_DRIVING, IO_4_MA); SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg1, PWRAP_SPI0_DRIVING, IO_6_MA);
SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg2, PWRAP_SPI1_DRIVING, IO_4_MA); SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg2, PWRAP_SPI1_DRIVING, IO_6_MA);
} }