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soc/amd/genoa/chipset.cb: enable dummy functions 

Enable the dummy function 0 that don't have an alias in the chipset
devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I607245c587a544007fd714f64901cbb50014612f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
This commit is contained in:
Felix Held 2023-12-07 23:16:47 +01:00
parent e78ea98bb2
commit 543c1ee314
1 changed files with 4 additions and 4 deletions
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8
src/soc/amd/genoa/chipset.cb
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@ -43,7 +43,7 @@ chip soc/amd/genoa
device pci 07.0 on end # Dummy device function, do not disable
device pci 07.1 alias gpp_bridge_0_a off # Internal GPP Bridge 0 to Bus B0
device pci 0.0 off end # Dummy PCIe function
device pci 0.0 on end # Dummy PCIe function
device pci 0.1 off end
device pci 0.2 alias primary_NTB_0 off end # Primary PCIe Non-TransparentBridge
device pci 0.3 alias secondry_NTB_0 off end # Secondary vNTB
@ -107,7 +107,7 @@ chip soc/amd/genoa
device pci 07.0 on end # Dummy device function, do not disable
device pci 07.1 alias gpp_bridge_1_a off
device pci 0.0 off end # Dummy PCIe function
device pci 0.0 on end # Dummy PCIe function
device pci 0.1 off end #SDXI
end
end
@ -148,7 +148,7 @@ chip soc/amd/genoa
device pci 07.0 on end # Dummy device function, do not disable
device pci 07.1 alias gpp_bridge_2_a off
device pci 0.0 off end # Dummy PCIe function
device pci 0.0 on end # Dummy PCIe function
device pci 0.1 off end
end
end
@ -193,7 +193,7 @@ chip soc/amd/genoa
device pci 07.0 on end # Dummy device function, do not disable
device pci 07.1 alias gpp_bridge_3_a off
device pci 0.0 off end # Dummy PCIe function
device pci 0.0 on end # Dummy PCIe function
device pci 0.1 off end #SDXI
device pci 0.2 alias primary_NTB_3 off end # Primary PCIe Non-TransparentBridge
device pci 0.3 alias secondry_NTB_3 off end # Secondary vNTB