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soc/skylake: Move IO decode range out from pch_lpc_init 

1. Move existing IO decode range from pch_lpc_init to early
   stage before SIO init.
2. At the same time, enable SIO decode range (0x2e/0x2f)
   for platform which use super IO.

Change-Id: I72df16d0a784686d8cadfbee09b5aef60576ac43
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/17337
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Teo Boon Tiong 2016-11-10 01:21:23 +08:00 committed by Martin Roth
parent 0068dfdcc8
commit 544dac692a
3 changed files with 18 additions and 11 deletions
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1
src/soc/intel/skylake/bootblock/bootblock.c
View File

@ -27,6 +27,7 @@ void bootblock_soc_early_init(void)
bootblock_systemagent_early_init();
bootblock_pch_early_init();
bootblock_cpu_init();
pch_early_iorange_init();
if (IS_ENABLED(CONFIG_UART_DEBUG))
pch_uart_init();

27
src/soc/intel/skylake/bootblock/pch.c
View File

@ -95,17 +95,6 @@ static void pch_enable_lpc(void)
/* Lookup device tree in romstage */
const struct device *dev;
const config_t *config;
u16 lpc_en;
/* IO Decode Range */
lpc_en = COMA_RANGE | (COMB_RANGE << 4);
pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, lpc_en);
pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOD, lpc_en);
/* IO Decode Enable */
lpc_en = COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN;
pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_en);
pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOE, lpc_en);
dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
if (!dev || !dev->chip_info)
@ -272,6 +261,22 @@ static void enable_heci(void)
pci_write_config8(dev, PCI_COMMAND, pcireg);
}
void pch_early_iorange_init(void)
{
/* Lookup device tree in romstage */
u16 lpc_en;
/* IO Decode Range */
lpc_en = COMA_RANGE | (COMB_RANGE << 4);
pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, lpc_en);
pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOD, lpc_en);
/* IO Decode Enable */
lpc_en = CNF1_LPC_EN | COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN;
pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_en);
pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOE, lpc_en);
}
void pch_early_init(void)
{
/*

1
src/soc/intel/skylake/include/soc/bootblock.h
View File

@ -32,6 +32,7 @@ void pch_uart_init(void);
void enable_smbus(void);
void i2c_early_init(void);
void pch_early_init(void);
void pch_early_iorange_init(void);
void report_platform_info(void);
void report_memory_config(void);
void set_max_freq(void);