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intel usbdebug: Add choice of EHCI controller 

Add option to choose one of the EHCI controllers in recent
intel chipsets for usbdebug use.

Since EHCI controller function changes from 0:1d.7 to 0:1d.0 in
rcba_config() for some mainboards, check the PCI class code
for match.

Change-Id: I18a78bf875427c163c857c6f0888935c1d2a58d4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3440
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kyösti Mälkki 2013-06-13 13:51:14 +03:00
parent 8101aa6bb0
commit 545b30d151
2 changed files with 31 additions and 2 deletions
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2
src/southbridge/intel/bd82x6x/Kconfig
View File

@ -30,7 +30,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_COMMON
select IOAPIC
select HAVE_HARD_RESET
select HAVE_USBDEBUG
select HAVE_USBDEBUG_OPTIONS
select HAVE_SMI_HANDLER
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM

31
src/southbridge/intel/common/usb_debug.c
View File

@ -28,7 +28,32 @@
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
return PCI_DEV(0, 0x1d, 7);
u32 class;
pci_devfn_t dev;
#if CONFIG_HAVE_USBDEBUG_OPTIONS
if (hcd_idx==2)
dev = PCI_DEV(0, 0x1a, 0);
else
dev = PCI_DEV(0, 0x1d, 0);
#else
dev = PCI_DEV(0, 0x1d, 7);
#endif
class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
#if CONFIG_HAVE_USBDEBUG_OPTIONS
if (class != PCI_EHCI_CLASSCODE) {
/* If we enter here before RCBA programming, EHCI function may
* appear with the highest function number instead.
*/
dev |= PCI_DEV(0, 0, 7);
class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
}
#endif
if (class != PCI_EHCI_CLASSCODE)
return 0;
return dev;
}
/* Required for successful build, but currently empty. */
@ -41,6 +66,10 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
u32 dbgctl;
/* Bail out. No console to complain in. */
if (!dev)
return;
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, base);