intel usbdebug: Add choice of EHCI controller
Add option to choose one of the EHCI controllers in recent intel chipsets for usbdebug use. Since EHCI controller function changes from 0:1d.7 to 0:1d.0 in rcba_config() for some mainboards, check the PCI class code for match. Change-Id: I18a78bf875427c163c857c6f0888935c1d2a58d4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3440 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
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@ -30,7 +30,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
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select SOUTHBRIDGE_INTEL_COMMON
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select IOAPIC
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select HAVE_HARD_RESET
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select HAVE_USBDEBUG
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select HAVE_USBDEBUG_OPTIONS
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select HAVE_SMI_HANDLER
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select USE_WATCHDOG_ON_BOOT
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select PCIEXP_ASPM
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@ -28,7 +28,32 @@
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pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
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{
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return PCI_DEV(0, 0x1d, 7);
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u32 class;
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pci_devfn_t dev;
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#if CONFIG_HAVE_USBDEBUG_OPTIONS
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if (hcd_idx==2)
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dev = PCI_DEV(0, 0x1a, 0);
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else
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dev = PCI_DEV(0, 0x1d, 0);
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#else
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dev = PCI_DEV(0, 0x1d, 7);
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#endif
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class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
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#if CONFIG_HAVE_USBDEBUG_OPTIONS
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if (class != PCI_EHCI_CLASSCODE) {
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/* If we enter here before RCBA programming, EHCI function may
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* appear with the highest function number instead.
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*/
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dev |= PCI_DEV(0, 0, 7);
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class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
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}
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#endif
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if (class != PCI_EHCI_CLASSCODE)
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return 0;
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return dev;
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}
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/* Required for successful build, but currently empty. */
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@ -41,6 +66,10 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
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{
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u32 dbgctl;
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/* Bail out. No console to complain in. */
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if (!dev)
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return;
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/* Set the EHCI BAR address. */
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pci_write_config32(dev, EHCI_BAR_INDEX, base);
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