mb/siemens/mc_ehl3: Use PSE GbE 0 instead of PSE GbE 1
As a result of hardware changes on this board, the PHY previously routed to the PSE GbE 1 is now routed to PSE GbE 0 on the Elkhart Lake SoC. This patch changes the device PCI ID in the board's devicetree and accordingly, the GPIO configuration. BUG=none TEST=Boot into Linux and observe whether both PSE GbE 0 and PCH GbE are working, while PSE GbE 1 remains inactive (not listed by 'ip link') . Change-Id: I322371f944d15134e6f48ecd84a4026c2fced27b Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit is contained in:
Jan Samek
Felix Held
parent
0458a4428d
commit
545c532902
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@ -184,7 +184,7 @@ chip soc/intel/elkhartlake
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device pci 1c.4 on end # RP5
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device pci 1d.0 off end # Intel PSE IPC (local host to PSE)
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device pci 1d.2 on # Intel PSE Time-Sensitive Networking GbE 1
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device pci 1d.1 on # Intel PSE Time-Sensitive Networking GbE 0
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# Enable external Marvell PHY 88E1512
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chip drivers/net/phy/m88e1512
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register "configure_leds" = "true"
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@ -195,7 +195,7 @@ chip soc/intel/elkhartlake
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# INTn is routed to LED[2] pin
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register "enable_int" = "true"
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register "downshift_cnt" = "2"
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device mdio 1 on # PHY address
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device mdio 0 on # PHY address
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ops m88e1512_ops
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end
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end
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@ -20,10 +20,10 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_B23, NONE, PLTRST, NF2), /* PCHHOT_N */
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/* Community 0 - GpioGroup GPP_T */
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PAD_NC(GPP_T4, NONE), /* Not connected */
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PAD_NC(GPP_T5, NONE), /* Not connected */
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PAD_NC(GPP_T6, NONE), /* Not connected */
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PAD_NC(GPP_T7, NONE), /* Not connected */
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PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), /* PSE_GBE0_INT */
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PAD_CFG_GPO(GPP_T5, 1, DEEP), /* PSE_GBE0_RST_N */
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PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */
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PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */
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PAD_CFG_NF(GPP_T12, NONE, DEEP, NF2), /* SIO_UART0_RXD */
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PAD_CFG_NF(GPP_T13, NONE, DEEP, NF2), /* SIO_UART0_TXD */
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@ -47,10 +47,10 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), /* EMMC_RESET */
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/* Community 1 - GpioGroup GPP_H */
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PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), /* PSE_GBE1_INT */
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PAD_CFG_GPO(GPP_H1, 1, DEEP), /* PSE_GBE1_RST_N */
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PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), /* PSE_GBE1_AUXTS */
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PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), /* PSE_GBE1_PPS */
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PAD_NC(GPP_H0, NONE), /* Not connected */
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PAD_NC(GPP_H1, NONE), /* Not connected */
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PAD_NC(GPP_H2, NONE), /* Not connected */
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PAD_NC(GPP_H3, NONE), /* Not connected */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), /* PCIE_CLKREQ4_N */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), /* PCIE_CLKREQ5_N */
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@ -80,36 +80,36 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_S1, NONE), /* Not connected */
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/* Community 3 - GpioGroup GPP_A */
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PAD_NC(GPP_A0, NONE), /* Not connected */
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PAD_NC(GPP_A1, NONE), /* Not connected */
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PAD_NC(GPP_A2, NONE), /* Not connected */
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PAD_NC(GPP_A3, NONE), /* Not connected */
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PAD_NC(GPP_A4, NONE), /* Not connected */
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PAD_NC(GPP_A5, NONE), /* Not connected */
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PAD_NC(GPP_A6, NONE), /* Not connected */
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PAD_NC(GPP_A7, NONE), /* Not connected */
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PAD_NC(GPP_A8, NONE), /* Not connected */
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PAD_NC(GPP_A9, NONE), /* Not connected */
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PAD_NC(GPP_A10, NONE), /* Not connected */
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PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD3 */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD2 */
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PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD1 */
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PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD0 */
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PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXCLK */
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PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXCTL */
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PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXCLK */
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXCTL */
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PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD3 */
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PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD2 */
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PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD1 */
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PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD0 */
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PAD_NC(GPP_A23, NONE), /* Not connected */
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PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD3 */
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PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD2 */
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PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD1 */
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PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD0 */
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PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCLK */
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PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCTL */
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCLK */
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PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD3 */
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PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD2 */
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PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD1 */
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PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD0 */
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PAD_NC(GPP_A11, NONE), /* Not connected */
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PAD_NC(GPP_A12, NONE), /* Not connected */
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PAD_NC(GPP_A13, NONE), /* Not connected */
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PAD_NC(GPP_A14, NONE), /* Not connected */
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PAD_NC(GPP_A15, NONE), /* Not connected */
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PAD_NC(GPP_A16, NONE), /* Not connected */
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PAD_NC(GPP_A17, NONE), /* Not connected */
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PAD_NC(GPP_A18, NONE), /* Not connected */
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PAD_NC(GPP_A19, NONE), /* Not connected */
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PAD_NC(GPP_A20, NONE), /* Not connected */
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PAD_NC(GPP_A21, NONE), /* Not connected */
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PAD_NC(GPP_A22, NONE), /* Not connected */
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PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCTL */
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/* Community 4 - GpioGroup GPP_C */
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PAD_NC(GPP_C3, NONE), /* Not connected */
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PAD_NC(GPP_C4, NONE), /* Not connected */
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PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */
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PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* PSE_GBE0_MDC */
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PSE_GBE0_MDIO */
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PAD_NC(GPP_C6, NONE), /* Not connected */
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PAD_NC(GPP_C7, NONE), /* Not connected */
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PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), /* SIO_UART1_RXD */
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PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4), /* SIO_UART1_TXD */
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GBE_MDIO */
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