drivers/i2c: Add i2c TPM support for different stages

Change-Id: Ib0839933f8b59f0c87cdda4e5374828bd6f1099f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/23759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This commit is contained in:
Philipp Deppenwiese 2018-02-14 16:47:12 +01:00 committed by Philipp Deppenwiese
parent 52acef175e
commit 545ed7ab3b
15 changed files with 21 additions and 0 deletions

View File

@ -4,5 +4,6 @@ bootblock-y += dw_i2c.c
romstage-y += dw_i2c.c
verstage-y += dw_i2c.c
ramstage-y += dw_i2c.c
postcar-y += dw_i2c.c
endif

View File

@ -32,6 +32,7 @@ romstage-y += cdp.c
romstage-y += chromeos.c
romstage-y += mmu.c
romstage-y += reset.c
romstage-y += blsp.c
ramstage-y += boardid.c
ramstage-y += cdp.c

View File

@ -30,6 +30,7 @@ romstage-y += cdp.c
romstage-y += chromeos.c
romstage-y += mmu.c
romstage-y += reset.c
romstage-y += gsbi.c
ramstage-y += boardid.c
ramstage-y += cdp.c

View File

@ -71,6 +71,7 @@ ramstage-y += sd.c
postcar-y += memmap.c
postcar-y += mmap_boot.c
postcar-y += spi.c
postcar-y += i2c.c
postcar-$(CONFIG_SOC_UART_DEBUG) += uart.c
postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S

View File

@ -65,6 +65,9 @@ smm-$(CONFIG_UART_DEBUG) += uart.c
postcar-y += memmap.c
postcar-y += pmutil.c
postcar-y += i2c.c
postcar-y += gspi.c
postcar-y += spi.c
postcar-$(CONFIG_UART_DEBUG) += uart.c
verstage-y += gspi.c

View File

@ -30,6 +30,7 @@ bootblock-$(CONFIG_TPM_CR50) += tpm_tis.c
verstage-$(CONFIG_TPM_CR50) += tpm_tis.c
romstage-$(CONFIG_TPM_CR50) += tpm_tis.c
ramstage-$(CONFIG_TPM_CR50) += tpm_tis.c
postcar-$(CONFIG_TPM_CR50) += tpm_tis.c
ifeq ($(CONFIG_MMA),y)
MMA_BLOBS_PATH = $(call strip_quotes,$(CONFIG_MMA_BLOBS_PATH))

View File

@ -3,6 +3,7 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_I2C),y)
bootblock-y += i2c.c
romstage-y += i2c.c
verstage-y += i2c.c
postcar-y += i2c.c
ramstage-y += i2c.c
endif

View File

@ -2,4 +2,5 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c

View File

@ -5,4 +5,5 @@ ramstage-y += pmc.c
ramstage-y += pmclib.c
smm-y += pmclib.c
verstage-y += pmclib.c
postcar-y += pmclib.c
endif

View File

@ -78,6 +78,7 @@ smm-$(CONFIG_UART_DEBUG) += uart.c
postcar-y += memmap.c
postcar-y += gspi.c
postcar-y += spi.c
postcar-y += i2c.c
postcar-$(CONFIG_UART_DEBUG) += uart.c
# cpu_microcode_bins += ???

View File

@ -50,6 +50,7 @@ romstage-$(CONFIG_SPI_FLASH) += flash_controller.c
romstage-y += ../common/pll.c pll.c
romstage-y += ../common/timer.c
romstage-y += timer.c
romstage-y += i2c.c
romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
romstage-y += ../common/cbmem.c

View File

@ -38,6 +38,9 @@ romstage-$(CONFIG_SPI_FLASH) += spi.c
romstage-y += timer.c
romstage-$(CONFIG_DRIVERS_UART) += uart.c
romstage-y += cbmem.c
romstage-y += i2c.c
romstage-y += blsp.c
romstage-y += qup.c
ramstage-y += blobs_init.c
ramstage-y += cbmem.c

View File

@ -37,6 +37,9 @@ romstage-$(CONFIG_SPI_FLASH) += spi.c
romstage-y += timer.c
romstage-$(CONFIG_DRIVERS_UART) += uart.c
romstage-y += cbmem.c
romstage-y += i2c.c
romstage-y += gsbi.c
romstage-y += qup.c
ramstage-y += blobs_init.c
ramstage-y += cbmem.c

View File

@ -54,6 +54,7 @@ romstage-y += sdram.c
romstage-y += ../common/rk808.c
romstage-y += ../common/pwm.c
romstage-y += tsadc.c
romstage-y += ../common/i2c.c
ramstage-y += soc.c
ramstage-y += ../common/cbmem.c

View File

@ -57,6 +57,7 @@ romstage-y += usb.c
romstage-y += gpio.c
romstage-y += saradc.c
romstage-y += ../common/gpio.c
romstage-y += ../common/i2c.c
################################################################################