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intel/braswell: fix build 

Commit "BCRD2: Enable LPDDR3" with the Change-Id listed below contained
additions to braswell's chip.h which were lost during merging.

BRANCH=None
BUG=None
TEST=google/strago builds

Change-Id: I995b788b6a308cefa23228544127bb1e384bbcc7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 561edf23ab696772fd0a6af34cb435db9d96e912
Original-Change-Id: Ie08900bc62d517394412cc597274fb8f5b6b0f51
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Original-Change-Id: I1cb5a03b77baf2df125b648dd75c9f8166f5571e
Original-Original-Signed-off-by: Jenny TC <jenny.tc@intel.com>
Original-Original-Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Original-Reviewed-on: https://chromium-review.googlesource.com/282155
Original-Reviewed-on: https://chromium-review.googlesource.com/288880
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/11065
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Jenny TC 2015-06-18 14:02:00 +05:30 committed by Patrick Georgi
parent 153ae105e5
commit 5468e94df1
1 changed files with 3 additions and 0 deletions
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3
src/soc/intel/braswell/chip.h
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@ -34,6 +34,9 @@
#define SVID_CONFIG3 3 #define SVID_CONFIG3 3
#define SVID_PMIC_CONFIG 8 #define SVID_PMIC_CONFIG 8
#define MEM_DDR3 0
#define MEM_LPDDR3 1
struct soc_intel_braswell_config { struct soc_intel_braswell_config {
uint8_t enable_xdp_tap; uint8_t enable_xdp_tap;
uint8_t clkreq_enable; uint8_t clkreq_enable;