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intel/fsp: Update Cannonlake FSP header 

Update Cannonlake FSP header to version 7.x.2A.20, the following changes
were made:
    1. Add MemtestonWarmBoot option.
    2. Add enable8254clockgatingonS3 option.
    3. Default disable Tccoffsetlock

BUG=None
TEST=None

Change-Id: Ie794960f0253b2a6dbd55ffda973756d15e35c01
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Lijian Zhao 2018-03-19 17:13:48 -07:00 committed by Patrick Georgi
parent a3ad990089
commit 5479525c74
2 changed files with 21 additions and 7 deletions
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10
src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
View File

@ -2291,9 +2291,15 @@ typedef struct {
**/ **/
UINT8 PegImrRpSelection; UINT8 PegImrRpSelection;
/** Offset 0x0513 /** Offset 0x0513 - Memory Test on Warm Boot
Run Base Memory Test on Warm Boot
0:Disable, 1:Enable
**/ **/
UINT8 ReservedFspmUpd[12]; UINT8 MemTestOnWarmBoot;
/** Offset 0x0514
**/
UINT8 ReservedFspmUpd[11];
} FSP_M_CONFIG; } FSP_M_CONFIG;
/** Fsp M Test Configuration /** Fsp M Test Configuration

18
src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
View File

@ -2154,9 +2154,17 @@ typedef struct {
**/ **/
UINT8 SataRstCpuAttachedStorage; UINT8 SataRstCpuAttachedStorage;
/** Offset 0x0752 /** Offset 0x0752 - Enable 8254 Static Clock Gating On S3
This is only applicable when Enable8254ClockGating is disabled. FSP will do the
8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
avoids the SMI requirement for the programming.
$EN_DIS
**/ **/
UINT8 UnusedUpdSpace25[2]; UINT8 Enable8254ClockGatingOnS3;
/** Offset 0x0753
**/
UINT8 UnusedUpdSpace25;
/** Offset 0x0754 - Pch PCIE device override table pointer /** Offset 0x0754 - Pch PCIE device override table pointer
The PCIe device table is being used to override PCIe device ASPM settings. This The PCIe device table is being used to override PCIe device ASPM settings. This
@ -2472,7 +2480,7 @@ typedef struct {
/** Offset 0x07DA - Tcc Offset Lock /** Offset 0x07DA - Tcc Offset Lock
Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
target; 0: Disabled; <b>1: Enabled </b>. target; <b>0: Disabled</b>; 1: Enabled.
$EN_DIS $EN_DIS
**/ **/
UINT8 TccOffsetLock; UINT8 TccOffsetLock;
@ -2886,13 +2894,13 @@ typedef struct {
/** Offset 0x0870 - Package PL4 power limit /** Offset 0x0870 - Package PL4 power limit
Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125 Range 0 to 1023875 in Step size of 125
**/ **/
UINT32 PowerLimit4; UINT32 PowerLimit4;
/** Offset 0x0874 - Tcc Offset Time Window for RATL /** Offset 0x0874 - Tcc Offset Time Window for RATL
Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125 Range 0 to 1023875 in Step size of 125
**/ **/
UINT32 TccOffsetTimeWindowForRatl; UINT32 TccOffsetTimeWindowForRatl;