Remove some white space and comment differences from devicetree.cb and Config.lb
files. These boards have non-trivial differences: gigabyte/m57sli kontron/986lcd-m dell/s1850 via/epia-m700 Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4924 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
parent
d63085b20e
commit
547d48ab01
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@ -136,7 +136,7 @@ config chip.h
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#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
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#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
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#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
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# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
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# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
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#Define gfx_dual_slot, 0: single slot, 1: dual slot
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#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
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#Define gfx_tmds, 0: didn't support TMDS, 1: support
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@ -136,7 +136,7 @@ config chip.h
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#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
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#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
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#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
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# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
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# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
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#Define gfx_dual_slot, 0: single slot, 1: dual slot
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#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
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#Define gfx_tmds, 0: didn't support TMDS, 1: support
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@ -1,29 +1,29 @@
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##
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##
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## This file is part of the coreboot project.
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##
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##
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## Copyright (C) 2007 AMD
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## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
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##
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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##
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## CONFIG_XIP_ROM_SIZE must be a power of 2.
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default CONFIG_XIP_ROM_SIZE = 64 * 1024
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include /config/failovercalculation.lb
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arch i386 end
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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@ -36,28 +36,28 @@ object get_bus_conf.o
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if CONFIG_GENERATE_MP_TABLE object mptable.o end
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if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
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if CONFIG_USE_INIT
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if CONFIG_USE_INIT
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makerule ./cache_as_ram_auto.o
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depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
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depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
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end
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else
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makerule ./cache_as_ram_auto.inc
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depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
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action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
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depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
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action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
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end
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end
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if CONFIG_USE_FAILOVER_IMAGE
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else
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if CONFIG_AP_CODE_IN_CAR
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makerule ./apc_auto.o
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depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
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end
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ldscript /arch/i386/init/ldscript_apc.lb
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makerule ./apc_auto.o
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depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
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end
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ldscript /arch/i386/init/ldscript_apc.lb
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end
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end
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@ -79,32 +79,32 @@ end
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mainboardinit cpu/x86/32bit/entry32.inc
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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##
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## Build our reset vector (This is where coreboot is entered)
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##
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if CONFIG_HAVE_FAILOVER_BOOT
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if CONFIG_USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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if CONFIG_USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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else
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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end
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@ -118,12 +118,12 @@ ldscript /southbridge/nvidia/mcp55/id.lds
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## ROMSTRAP table for MCP55
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##
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if CONFIG_HAVE_FAILOVER_BOOT
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if CONFIG_USE_FAILOVER_IMAGE
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if CONFIG_USE_FAILOVER_IMAGE
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mainboardinit southbridge/nvidia/mcp55/romstrap.inc
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ldscript /southbridge/nvidia/mcp55/romstrap.lds
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end
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else
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if CONFIG_USE_FALLBACK_IMAGE
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit southbridge/nvidia/mcp55/romstrap.inc
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ldscript /southbridge/nvidia/mcp55/romstrap.lds
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end
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@ -135,7 +135,7 @@ end
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mainboardinit cpu/amd/car/cache_as_ram.inc
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###
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### This is the early phase of coreboot startup
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### This is the early phase of coreboot startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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@ -176,209 +176,187 @@ if CONFIG_GENERATE_ACPI_TABLES
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end
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##
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## Include the secondary Configuration files
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## Include the secondary Configuration files
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##
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config chip.h
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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chip cpu/amd/socket_AM2
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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chip northbridge/amd/amdk8 #mc0
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device pci 18.0 on
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# devices on link 0, link 0 == LDT 0
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chip southbridge/nvidia/mcp55
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device pci 0.0 on end # HT
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device pci 1.0 on # LPC
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chip superio/ite/it8716f
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# Floppy and any LDN
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device pnp 2e.0 on
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# Watchdog from CLKIN, CLKIN = 24 MHz
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irq 0x23 = 0x11
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device apic_cluster 0 on
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chip cpu/amd/socket_AM2
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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chip northbridge/amd/amdk8 #mc0
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device pci 18.0 on # devices on link 0, link 0 == LDT 0
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chip southbridge/nvidia/mcp55
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device pci 0.0 on end # HT
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device pci 1.0 on # LPC
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chip superio/ite/it8716f
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# Floppy and any LDN
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device pnp 2e.0 on
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# Watchdog from CLKIN, CLKIN = 24 MHz
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irq 0x23 = 0x11
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# Serial Flash (SPI only)
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#0x24 = 0x1a
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.2 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.4 on # EC
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io 0x60 = 0x290
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io 0x62 = 0x230
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irq 0x70 = 9
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.6 on # Mouse
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irq 0x70 = 12
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end
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device pnp 2e.7 on # GPIO, SPI flash
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# pin 84 is not GP10
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irq 0x25 = 0x0
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# pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
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irq 0x26 = 0x43
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# pin 13 is GP35
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irq 0x27 = 0x20
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# pin 70 is not GP46
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#irq 0x28 = 0x0
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# pin 6,3,128,127,126 is GP63,64,65,66,67
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irq 0x29 = 0x81
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# Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
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#irq 0x2c = 0x1f
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# Simple I/O base
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io 0x62 = 0x800
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# Serial Flash I/O (SPI only)
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io 0x64 = 0x820
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# watch dog force timeout (parallel flash only)
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#irq 0x71 = 0x1
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# No WDT interrupt
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irq 0x72 = 0x0
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# GPIO pin set 1 disable internal pullup
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irq 0xb8 = 0x0
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# GPIO pin set 5 enable internal pullup
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irq 0xbc = 0x01
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# SIO pin set 1 alternate function
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#irq 0xc0 = 0x0
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# SIO pin set 2 mixed function
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irq 0xc1 = 0x43
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# SIO pin set 3 mixed function
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irq 0xc2 = 0x20
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# SIO pin set 4 alternate function
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#irq 0xc3 = 0x0
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# SIO pin set 1 input mode
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#irq 0xc8 = 0x0
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# SIO pin set 2 input mode
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irq 0xc9 = 0x0
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# SIO pin set 4 input mode
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#irq 0xcb = 0x0
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# Generate SMI# on EC IRQ
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#irq 0xf0 = 0x10
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# SMI# level trigger
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#irq 0xf1 = 0x40
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# HWMON alert beep pin location
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irq 0xf6 = 0x28
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end
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device pnp 2e.8 off # MIDI
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io 0x60 = 0x300
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irq 0x70 = 10
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end
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device pnp 2e.9 off # GAME
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io 0x60 = 0x220
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end
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device pnp 2e.a off end # CIR
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#0x24 = 0x1a
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.2 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.4 on # EC
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io 0x60 = 0x290
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io 0x62 = 0x230
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irq 0x70 = 9
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.6 on # Mouse
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irq 0x70 = 12
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end
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device pnp 2e.7 on # GPIO, SPI flash
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# pin 84 is not GP10
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irq 0x25 = 0x0
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# pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
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irq 0x26 = 0x43
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# pin 13 is GP35
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irq 0x27 = 0x20
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# pin 70 is not GP46
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#irq 0x28 = 0x0
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# pin 6,3,128,127,126 is GP63,64,65,66,67
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irq 0x29 = 0x81
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# Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
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#irq 0x2c = 0x1f
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# Simple I/O base
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io 0x62 = 0x800
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# Serial Flash I/O (SPI only)
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io 0x64 = 0x820
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# watch dog force timeout (parallel flash only)
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#irq 0x71 = 0x1
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# No WDT interrupt
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irq 0x72 = 0x0
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# GPIO pin set 1 disable internal pullup
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irq 0xb8 = 0x0
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# GPIO pin set 5 enable internal pullup
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irq 0xbc = 0x01
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# SIO pin set 1 alternate function
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#irq 0xc0 = 0x0
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# SIO pin set 2 mixed function
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irq 0xc1 = 0x43
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# SIO pin set 3 mixed function
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irq 0xc2 = 0x20
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# SIO pin set 4 alternate function
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#irq 0xc3 = 0x0
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# SIO pin set 1 input mode
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#irq 0xc8 = 0x0
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# SIO pin set 2 input mode
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irq 0xc9 = 0x0
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# SIO pin set 4 input mode
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#irq 0xcb = 0x0
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# Generate SMI# on EC IRQ
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#irq 0xf0 = 0x10
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# SMI# level trigger
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#irq 0xf1 = 0x40
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# HWMON alert beep pin location
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irq 0xf6 = 0x28
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end
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device pnp 2e.8 off # MIDI
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io 0x60 = 0x300
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irq 0x70 = 10
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end
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device pnp 2e.9 off # GAME
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io 0x60 = 0x220
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end
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device pnp 2e.a off end # CIR
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end
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device pci 1.1 on # SM 0
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chip drivers/generic/generic #dimm 0-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic #dimm 0-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic #dimm 0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic #dimm 0-1-1
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device i2c 53 on end
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end
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chip drivers/generic/generic #dimm 1-0-0
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device i2c 54 on end
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end
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chip drivers/generic/generic #dimm 1-0-1
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device i2c 55 on end
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end
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chip drivers/generic/generic #dimm 1-1-0
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device i2c 56 on end
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end
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chip drivers/generic/generic #dimm 1-1-1
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device i2c 57 on end
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end
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end # SM
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end
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device pci 1.1 on # SM 0
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chip drivers/generic/generic #dimm 0-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic #dimm 0-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic #dimm 0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic #dimm 0-1-1
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device i2c 53 on end
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end
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chip drivers/generic/generic #dimm 1-0-0
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device i2c 54 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-1
|
||||
device i2c 55 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-0
|
||||
device i2c 56 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-1
|
||||
device i2c 57 on end
|
||||
end
|
||||
end # SM
|
||||
#WTF?!? We already have device pci 1.1 in the section above
|
||||
device pci 1.1 on # SM 1
|
||||
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
|
||||
# chip drivers/generic/generic #PCIXA Slot1
|
||||
# device i2c 50 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #PCIXB Slot1
|
||||
# device i2c 51 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #PCIXB Slot2
|
||||
# device i2c 52 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #PCI Slot1
|
||||
# device i2c 53 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #Master MCP55 PCI-E
|
||||
# device i2c 54 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #Slave MCP55 PCI-E
|
||||
# device i2c 55 on end
|
||||
# end
|
||||
chip drivers/generic/generic #MAC EEPROM
|
||||
device i2c 51 on end
|
||||
end
|
||||
|
||||
end # SM
|
||||
device pci 2.0 on end # USB 1.1
|
||||
device pci 2.1 on end # USB 2
|
||||
device pci 4.0 on end # IDE
|
||||
device pci 5.0 on end # SATA 0
|
||||
device pci 5.1 on end # SATA 1
|
||||
device pci 5.2 on end # SATA 2
|
||||
device pci 6.0 on end # PCI
|
||||
device pci 6.1 on end # AZA
|
||||
device pci 8.0 on end # NIC
|
||||
device pci 9.0 off end # NIC
|
||||
device pci a.0 on end # PCI E 5
|
||||
device pci b.0 on end # PCI E 4
|
||||
device pci c.0 on end # PCI E 3
|
||||
device pci d.0 on end # PCI E 2
|
||||
device pci e.0 on end # PCI E 1
|
||||
device pci f.0 on end # PCI E 0
|
||||
register "ide0_enable" = "1"
|
||||
register "sata0_enable" = "1"
|
||||
register "sata1_enable" = "1"
|
||||
device pci 1.1 on # SM 1
|
||||
chip drivers/generic/generic #MAC EEPROM
|
||||
device i2c 51 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 2.0 on end # USB 1.1
|
||||
device pci 2.1 on end # USB 2
|
||||
device pci 4.0 on end # IDE
|
||||
device pci 5.0 on end # SATA 0
|
||||
device pci 5.1 on end # SATA 1
|
||||
device pci 5.2 on end # SATA 2
|
||||
device pci 6.0 on end # PCI
|
||||
device pci 6.1 on end # AZA
|
||||
device pci 8.0 on end # NIC
|
||||
device pci 9.0 off end # NIC
|
||||
device pci a.0 on end # PCI E 5
|
||||
device pci b.0 on end # PCI E 4
|
||||
device pci c.0 on end # PCI E 3
|
||||
device pci d.0 on end # PCI E 2
|
||||
device pci e.0 on end # PCI E 1
|
||||
device pci f.0 on end # PCI E 0
|
||||
register "ide0_enable" = "1"
|
||||
register "sata0_enable" = "1"
|
||||
register "sata1_enable" = "1"
|
||||
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
|
||||
register "mac_eeprom_addr" = "0x51"
|
||||
end
|
||||
end # device pci 18.0
|
||||
end #device pci 18.0
|
||||
device pci 18.0 on end # Link 1
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end # mc0
|
||||
|
||||
end # PCI domain
|
||||
|
||||
# chip drivers/generic/debug
|
||||
# device pnp 0.0 off end # chip name
|
||||
# device pnp 0.1 on end # pci_regs_all
|
||||
# device pnp 0.2 on end # mem
|
||||
# device pnp 0.3 off end # cpuid
|
||||
# device pnp 0.4 on end # smbus_regs_all
|
||||
# device pnp 0.5 off end # dual core msr
|
||||
# device pnp 0.6 off end # cache size
|
||||
# device pnp 0.7 off end # tsc
|
||||
# device pnp 0.8 off end # io
|
||||
# device pnp 0.9 off end # io
|
||||
# end
|
||||
|
||||
# chip drivers/generic/debug
|
||||
# device pnp 0.0 off end # chip name
|
||||
# device pnp 0.1 on end # pci_regs_all
|
||||
# device pnp 0.2 on end # mem
|
||||
# device pnp 0.3 off end # cpuid
|
||||
# device pnp 0.4 on end # smbus_regs_all
|
||||
# device pnp 0.5 off end # dual core msr
|
||||
# device pnp 0.6 off end # cache size
|
||||
# device pnp 0.7 off end # tsc
|
||||
# device pnp 0.8 off end # io
|
||||
# device pnp 0.9 off end # io
|
||||
# end
|
||||
end #root_complex
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ chip northbridge/amd/amdk8/root_complex
|
|||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 18.0 on
|
||||
chip southbridge/nvidia/mcp55
|
||||
device pci 0.0 on end
|
||||
device pci 1.0 on
|
||||
chip northbridge/amd/amdk8 #mc0
|
||||
device pci 18.0 on # devices on link 0, link 0 == LDT 0
|
||||
chip southbridge/nvidia/mcp55
|
||||
device pci 0.0 on end # HT
|
||||
device pci 1.0 on # LPC
|
||||
chip superio/ite/it8716f
|
||||
# Floppy and any LDN
|
||||
device pnp 2e.0 on
|
||||
|
|
@ -52,7 +52,7 @@ device pci_domain 0 on
|
|||
# pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
|
||||
irq 0x26 = 0x43
|
||||
# pin 13 is GP35
|
||||
irq 0x27 = 0x20
|
||||
irq 0x27 = 0x20
|
||||
# pin 70 is not GP46
|
||||
#irq 0x28 = 0x0
|
||||
# pin 6,3,128,127,126 is GP63,64,65,66,67
|
||||
|
|
@ -66,7 +66,7 @@ device pci_domain 0 on
|
|||
# watch dog force timeout (parallel flash only)
|
||||
#irq 0x71 = 0x1
|
||||
# No WDT interrupt
|
||||
irq 0x72 = 0x0
|
||||
irq 0x72 = 0x0
|
||||
# GPIO pin set 1 disable internal pullup
|
||||
irq 0xb8 = 0x0
|
||||
# GPIO pin set 5 enable internal pullup
|
||||
|
|
@ -99,11 +99,10 @@ device pci_domain 0 on
|
|||
device pnp 2e.9 off # GAME
|
||||
io 0x60 = 0x220
|
||||
end
|
||||
device pnp 2e.a off # CIR
|
||||
end
|
||||
device pnp 2e.a off end # CIR
|
||||
end
|
||||
end
|
||||
device pci 1.1 on
|
||||
device pci 1.1 on # SM 0
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
|
|
@ -129,22 +128,22 @@ device pci_domain 0 on
|
|||
device i2c 57 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 2.0 on end # USB 1.1
|
||||
device pci 2.1 on end # USB 2
|
||||
device pci 4.0 on end # IDE
|
||||
device pci 5.0 on end # SATA 0
|
||||
device pci 5.1 on end # SATA 1
|
||||
device pci 5.2 on end # SATA 2
|
||||
device pci 6.0 on end # PCI
|
||||
device pci 6.1 on end # AUDIO
|
||||
device pci 8.0 on end # NIC
|
||||
device pci 9.0 off end # N/A
|
||||
device pci a.0 on end # PCI E 5
|
||||
device pci b.0 on end # PCI E 4
|
||||
device pci c.0 on end # PCI E 3
|
||||
device pci d.0 on end # PCI E 2
|
||||
device pci e.0 on end # PCI E 1
|
||||
device pci f.0 on end # PCI E 0
|
||||
device pci 2.0 on end # USB 1.1
|
||||
device pci 2.1 on end # USB 2
|
||||
device pci 4.0 on end # IDE
|
||||
device pci 5.0 on end # SATA 0
|
||||
device pci 5.1 on end # SATA 1
|
||||
device pci 5.2 on end # SATA 2
|
||||
device pci 6.0 on end # PCI
|
||||
device pci 6.1 on end # AUDIO
|
||||
device pci 8.0 on end # NIC
|
||||
device pci 9.0 off end # N/A
|
||||
device pci a.0 on end # PCI E 5
|
||||
device pci b.0 on end # PCI E 4
|
||||
device pci c.0 on end # PCI E 3
|
||||
device pci d.0 on end # PCI E 2
|
||||
device pci e.0 on end # PCI E 1
|
||||
device pci f.0 on end # PCI E 0
|
||||
register "ide0_enable" = "1"
|
||||
register "sata0_enable" = "1"
|
||||
register "sata1_enable" = "1"
|
||||
|
|
@ -153,13 +152,14 @@ device pci_domain 0 on
|
|||
end
|
||||
end #device pci 18.0
|
||||
device pci 18.0 on end # Link 1
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end # mc0
|
||||
end # PCI domain
|
||||
|
||||
# chip drivers/generic/debug
|
||||
# chip drivers/generic/debug
|
||||
# device pnp 0.0 off end # chip name
|
||||
# device pnp 0.1 on end # pci_regs_all
|
||||
# device pnp 0.2 on end # mem
|
||||
|
|
@ -170,6 +170,5 @@ device pci_domain 0 on
|
|||
# device pnp 0.7 off end # tsc
|
||||
# device pnp 0.8 off end # io
|
||||
# device pnp 0.9 off end # io
|
||||
# end
|
||||
|
||||
# end
|
||||
end #root_complex
|
||||
|
|
|
|||
|
|
@ -136,7 +136,7 @@ config chip.h
|
|||
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
|
||||
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
|
||||
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
|
||||
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
|
||||
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
|
||||
#Define gfx_dual_slot, 0: single slot, 1: dual slot
|
||||
#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
|
||||
#Define gfx_tmds, 0: didn't support TMDS, 1: support
|
||||
|
|
|
|||
Loading…
Reference in New Issue