sb/intel/ibexpeak: Use common Intel SMM code
TODO in followup patch: Some not mainboard specific things should be moved out of mainboard_smi_apmc. Change-Id: Ifc2d8f7755ace598e66b162d071d472093e4656e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Arthur Heymans
parent
608d73e4c5
commit
548f33a9f4
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@ -19,7 +19,7 @@
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <southbridge/intel/ibexpeak/nvs.h>
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#include <southbridge/intel/ibexpeak/pch.h>
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#include <southbridge/intel/common/pmutil.h>
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#include <southbridge/intel/ibexpeak/me.h>
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#include <southbridge/intel/common/finalize.h>
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#include <northbridge/intel/nehalem/nehalem.h>
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@ -18,9 +18,9 @@
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#include <cpu/x86/smm.h>
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#include <device/pci_ops.h>
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#include <southbridge/intel/ibexpeak/nvs.h>
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#include <southbridge/intel/ibexpeak/pch.h>
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#include <southbridge/intel/ibexpeak/me.h>
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#include <southbridge/intel/common/finalize.h>
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#include <southbridge/intel/common/pmutil.h>
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#include <northbridge/intel/nehalem/nehalem.h>
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#include <cpu/intel/model_2065x/model_2065x.h>
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#include <ec/acpi/ec.h>
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@ -32,6 +32,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
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select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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select SOUTHBRIDGE_INTEL_COMMON_SPI
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select SOUTHBRIDGE_INTEL_COMMON_SMM
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select HAVE_USBDEBUG_OPTIONS
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select COMMON_FADT
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select ACPI_SATA_GENERATOR
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@ -35,7 +35,6 @@ ramstage-y += ../bd82x6x/me_status.c
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ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c
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ramstage-y += madt.c
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ramstage-y += smi.c
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smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/pch.c
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romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../common/gpio.c early_thermal.c
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@ -61,7 +61,6 @@ int pch_silicon_revision(void);
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int pch_silicon_type(void);
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int pch_silicon_supported(int type, int rev);
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void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
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void gpi_route_interrupt(u8 gpi, u8 mode);
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#if CONFIG(ELOG)
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void pch_log_state(void);
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#endif
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@ -1,347 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define __SIMPLE_DEVICE__
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#include <device/device.h>
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#include <device/pci.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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#include <cpu/intel/smm/gen1/smi.h>
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#include "pch.h"
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/* While we read PMBASE dynamically in case it changed, let's
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* initialize it with a sane value
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*/
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static u16 pmbase = DEFAULT_PMBASE;
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/**
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* @brief read and clear PM1_STS
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* @return PM1_STS register
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*/
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static u16 reset_pm1_status(void)
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{
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u16 reg16;
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reg16 = inw(pmbase + PM1_STS);
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/* set status bits are cleared by writing 1 to them */
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outw(reg16, pmbase + PM1_STS);
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return reg16;
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}
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static void dump_pm1_status(u16 pm1_sts)
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{
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printk(BIOS_DEBUG, "PM1_STS: ");
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if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");
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if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");
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if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");
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if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");
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if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN ");
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if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL ");
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if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM ");
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if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF ");
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printk(BIOS_DEBUG, "\n");
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}
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/**
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* @brief read and clear SMI_STS
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* @return SMI_STS register
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*/
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static u32 reset_smi_status(void)
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{
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u32 reg32;
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reg32 = inl(pmbase + SMI_STS);
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/* set status bits are cleared by writing 1 to them */
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outl(reg32, pmbase + SMI_STS);
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return reg32;
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}
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static void dump_smi_status(u32 smi_sts)
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{
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printk(BIOS_DEBUG, "SMI_STS: ");
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if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
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if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
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if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
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if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
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if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
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if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
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if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
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if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
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if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
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if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
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if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
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if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
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if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
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if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
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if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
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if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
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if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
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if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
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if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
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if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
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printk(BIOS_DEBUG, "\n");
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}
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/**
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* @brief read and clear GPE0_STS
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* @return GPE0_STS register
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*/
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static u32 reset_gpe0_status(void)
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{
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u32 reg32;
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reg32 = inl(pmbase + GPE0_STS);
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/* set status bits are cleared by writing 1 to them */
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outl(reg32, pmbase + GPE0_STS);
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return reg32;
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}
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static void dump_gpe0_status(u32 gpe0_sts)
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{
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int i;
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printk(BIOS_DEBUG, "GPE0_STS: ");
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for (i=31; i>= 16; i--) {
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if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
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}
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if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
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if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
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if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
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if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
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if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
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if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
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if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
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if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
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if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
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if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
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if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
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if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
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if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");
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if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
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printk(BIOS_DEBUG, "\n");
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}
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/**
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* @brief read and clear ALT_GP_SMI_STS
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* @return ALT_GP_SMI_STS register
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*/
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static u16 reset_alt_gp_smi_status(void)
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{
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u16 reg16;
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reg16 = inl(pmbase + ALT_GP_SMI_STS);
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/* set status bits are cleared by writing 1 to them */
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outl(reg16, pmbase + ALT_GP_SMI_STS);
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return reg16;
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}
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static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
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{
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int i;
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printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");
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for (i=15; i>= 0; i--) {
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if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", i);
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}
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printk(BIOS_DEBUG, "\n");
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}
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/**
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* @brief read and clear TCOx_STS
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* @return TCOx_STS registers
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*/
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static u32 reset_tco_status(void)
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{
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u32 tcobase = pmbase + 0x60;
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u32 reg32;
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reg32 = inl(tcobase + 0x04);
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/* set status bits are cleared by writing 1 to them */
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outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
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if (reg32 & (1 << 18))
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outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS
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return reg32;
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}
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static void dump_tco_status(u32 tco_sts)
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{
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printk(BIOS_DEBUG, "TCO_STS: ");
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if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
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if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
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if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
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if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
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if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
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if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
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if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
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if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
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if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
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if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
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if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
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if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
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if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
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printk(BIOS_DEBUG, "\n");
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}
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/**
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* @brief Set the EOS bit
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*/
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static void smi_set_eos(void)
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{
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u8 reg8;
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reg8 = inb(pmbase + SMI_EN);
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reg8 |= EOS;
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outb(reg8, pmbase + SMI_EN);
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}
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void southbridge_smm_init(void)
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{
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u32 smi_en;
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u16 pm1_en;
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u32 gpe0_en;
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#if CONFIG(ELOG)
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/* Log events from chipset before clearing */
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pch_log_state();
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#endif
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printk(BIOS_DEBUG, "Initializing southbridge SMI...");
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pmbase = pci_read_config32(PCI_DEV(0, 0x1f, 0),
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PMBASE) & 0xff80;
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
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smi_en = inl(pmbase + SMI_EN);
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if (smi_en & APMC_EN) {
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printk(BIOS_INFO, "SMI# handler already enabled?\n");
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return;
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}
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printk(BIOS_DEBUG, "\n");
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dump_smi_status(reset_smi_status());
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dump_pm1_status(reset_pm1_status());
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dump_gpe0_status(reset_gpe0_status());
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dump_alt_gp_smi_status(reset_alt_gp_smi_status());
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dump_tco_status(reset_tco_status());
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/* Disable GPE0 PME_B0 */
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gpe0_en = inl(pmbase + GPE0_EN);
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gpe0_en &= ~PME_B0_EN;
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outl(gpe0_en, pmbase + GPE0_EN);
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pm1_en = 0;
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pm1_en |= PWRBTN_EN;
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pm1_en |= GBL_EN;
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outw(pm1_en, pmbase + PM1_EN);
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/* Enable SMI generation:
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* - on TCO events
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* - on APMC writes (io 0xb2)
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* - on writes to SLP_EN (sleep states)
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* - on writes to GBL_RLS (bios commands)
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* No SMIs:
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* - on microcontroller writes (io 0x62/0x66)
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*/
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smi_en = 0; /* reset SMI enables */
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#if 0
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smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN;
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#endif
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smi_en |= TCO_EN;
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smi_en |= APMC_EN;
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#if DEBUG_PERIODIC_SMIS
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/* Set DEBUG_PERIODIC_SMIS in pch.h to debug using
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* periodic SMIs.
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*/
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smi_en |= PERIODIC_EN;
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#endif
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smi_en |= SLP_SMI_EN;
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#if 0
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smi_en |= BIOS_EN;
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#endif
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/* The following need to be on for SMIs to happen */
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smi_en |= EOS | GBL_SMI_EN;
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outl(smi_en, pmbase + SMI_EN);
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}
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void southbridge_trigger_smi(void)
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{
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/**
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* There are several methods of raising a controlled SMI# via
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* software, among them:
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* - Writes to io 0xb2 (APMC)
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* - Writes to the Local Apic ICR with Delivery mode SMI.
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*
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* Using the local apic is a bit more tricky. According to
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* AMD Family 11 Processor BKDG no destination shorthand must be
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* used.
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* The whole SMM initialization is quite a bit hardware specific, so
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* I'm not too worried about the better of the methods at the moment
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*/
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/* raise an SMI interrupt */
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printk(BIOS_SPEW, " ... raise SMI#\n");
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outb(0x00, 0xb2);
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}
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void southbridge_clear_smi_status(void)
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{
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/* Clear SMI status */
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reset_smi_status();
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/* Clear PM1 status */
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reset_pm1_status();
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/* Set EOS bit so other SMIs can occur. */
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smi_set_eos();
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}
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void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
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{
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/*
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* Issue SMI to set the gnvs pointer in SMM.
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* tcg and smi1 are unused.
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*
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* EAX = APM_CNT_GNVS_UPDATE
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* EBX = gnvs pointer
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* EDX = APM_CNT
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*/
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asm volatile (
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"outb %%al, %%dx\n\t"
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: /* ignore result */
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: "a" (APM_CNT_GNVS_UPDATE),
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"b" ((u32)gnvs),
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"d" (APM_CNT)
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);
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}
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@ -35,13 +35,7 @@
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*/
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#include <northbridge/intel/nehalem/nehalem.h>
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#include <southbridge/intel/common/gpio.h>
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/* While we read PMBASE dynamically in case it changed, let's
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* initialize it with a sane value
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*/
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static u16 pmbase = DEFAULT_PMBASE;
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static u8 smm_initialized = 0;
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#include <southbridge/intel/common/pmutil.h>
|
||||
|
||||
/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
|
||||
* by coreboot.
|
||||
|
|
@ -52,193 +46,6 @@ global_nvs_t *smm_get_gnvs(void)
|
|||
return gnvs;
|
||||
}
|
||||
|
||||
static void alt_gpi_mask(u16 clr, u16 set)
|
||||
{
|
||||
u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN);
|
||||
alt_gp &= ~clr;
|
||||
alt_gp |= set;
|
||||
outw(alt_gp, pmbase + ALT_GP_SMI_EN);
|
||||
}
|
||||
|
||||
static void gpe0_mask(u32 clr, u32 set)
|
||||
{
|
||||
u32 gpe0 = inl(pmbase + GPE0_EN);
|
||||
gpe0 &= ~clr;
|
||||
gpe0 |= set;
|
||||
outl(gpe0, pmbase + GPE0_EN);
|
||||
}
|
||||
|
||||
void gpi_route_interrupt(u8 gpi, u8 mode)
|
||||
{
|
||||
u32 gpi_rout;
|
||||
if (gpi >= 16)
|
||||
return;
|
||||
|
||||
alt_gpi_mask(1 << gpi, 0);
|
||||
gpe0_mask(1 << (gpi+16), 0);
|
||||
|
||||
gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
|
||||
gpi_rout &= ~(3 << (2 * gpi));
|
||||
gpi_rout |= ((mode & 3) << (2 * gpi));
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout);
|
||||
|
||||
if (mode == GPI_IS_SCI)
|
||||
gpe0_mask(0, 1 << (gpi+16));
|
||||
else if (mode == GPI_IS_SMI)
|
||||
alt_gpi_mask(0, 1 << gpi);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief read and clear PM1_STS
|
||||
* @return PM1_STS register
|
||||
*/
|
||||
static u16 reset_pm1_status(void)
|
||||
{
|
||||
u16 reg16;
|
||||
|
||||
reg16 = inw(pmbase + PM1_STS);
|
||||
/* set status bits are cleared by writing 1 to them */
|
||||
outw(reg16, pmbase + PM1_STS);
|
||||
|
||||
return reg16;
|
||||
}
|
||||
|
||||
static void dump_pm1_status(u16 pm1_sts)
|
||||
{
|
||||
printk(BIOS_SPEW, "PM1_STS: ");
|
||||
if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
|
||||
if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
|
||||
if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
|
||||
if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
|
||||
if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN ");
|
||||
if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL ");
|
||||
if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM ");
|
||||
if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF ");
|
||||
printk(BIOS_SPEW, "\n");
|
||||
int reg16 = inw(pmbase + PM1_EN);
|
||||
printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief read and clear SMI_STS
|
||||
* @return SMI_STS register
|
||||
*/
|
||||
static u32 reset_smi_status(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
reg32 = inl(pmbase + SMI_STS);
|
||||
/* set status bits are cleared by writing 1 to them */
|
||||
outl(reg32, pmbase + SMI_STS);
|
||||
|
||||
return reg32;
|
||||
}
|
||||
|
||||
static void dump_smi_status(u32 smi_sts)
|
||||
{
|
||||
printk(BIOS_DEBUG, "SMI_STS: ");
|
||||
if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
|
||||
if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
|
||||
if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
|
||||
if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
|
||||
if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
|
||||
if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
|
||||
if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
|
||||
if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
|
||||
if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
|
||||
if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
|
||||
if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
|
||||
if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
|
||||
if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
|
||||
if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
|
||||
if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
|
||||
if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
|
||||
if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
|
||||
if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
|
||||
if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief read and clear GPE0_STS
|
||||
* @return GPE0_STS register
|
||||
*/
|
||||
static u32 reset_gpe0_status(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
reg32 = inl(pmbase + GPE0_STS);
|
||||
/* set status bits are cleared by writing 1 to them */
|
||||
outl(reg32, pmbase + GPE0_STS);
|
||||
|
||||
return reg32;
|
||||
}
|
||||
|
||||
static void dump_gpe0_status(u32 gpe0_sts)
|
||||
{
|
||||
int i;
|
||||
printk(BIOS_DEBUG, "GPE0_STS: ");
|
||||
for (i=31; i>= 16; i--) {
|
||||
if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
|
||||
}
|
||||
if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
|
||||
if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
|
||||
if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
|
||||
if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
|
||||
if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "BATLOW ");
|
||||
if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
|
||||
if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
|
||||
if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
|
||||
if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
|
||||
if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
|
||||
if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
|
||||
if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
|
||||
if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE ");
|
||||
if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOTPLUG ");
|
||||
if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief read and clear TCOx_STS
|
||||
* @return TCOx_STS registers
|
||||
*/
|
||||
static u32 reset_tco_status(void)
|
||||
{
|
||||
u32 tcobase = pmbase + 0x60;
|
||||
u32 reg32;
|
||||
|
||||
reg32 = inl(tcobase + 0x04);
|
||||
/* set status bits are cleared by writing 1 to them */
|
||||
outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
|
||||
if (reg32 & (1 << 18))
|
||||
outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS
|
||||
|
||||
return reg32;
|
||||
}
|
||||
|
||||
|
||||
static void dump_tco_status(u32 tco_sts)
|
||||
{
|
||||
printk(BIOS_DEBUG, "TCO_STS: ");
|
||||
if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
|
||||
if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
|
||||
if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
|
||||
if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
|
||||
if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
|
||||
if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
|
||||
if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
|
||||
if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
|
||||
if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
|
||||
if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
|
||||
if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
|
||||
if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
|
||||
if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
int southbridge_io_trap_handler(int smif)
|
||||
{
|
||||
switch (smif) {
|
||||
|
|
@ -256,53 +63,6 @@ int southbridge_io_trap_handler(int smif)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the EOS bit
|
||||
*/
|
||||
void southbridge_smi_set_eos(void)
|
||||
{
|
||||
u8 reg8;
|
||||
|
||||
reg8 = inb(pmbase + SMI_EN);
|
||||
reg8 |= EOS;
|
||||
outb(reg8, pmbase + SMI_EN);
|
||||
}
|
||||
|
||||
static void busmaster_disable_on_bus(int bus)
|
||||
{
|
||||
int slot, func;
|
||||
unsigned int val;
|
||||
unsigned char hdr;
|
||||
|
||||
for (slot = 0; slot < 0x20; slot++) {
|
||||
for (func = 0; func < 8; func++) {
|
||||
u32 reg32;
|
||||
pci_devfn_t dev = PCI_DEV(bus, slot, func);
|
||||
|
||||
val = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
|
||||
if (val == 0xffffffff || val == 0x00000000 ||
|
||||
val == 0x0000ffff || val == 0xffff0000)
|
||||
continue;
|
||||
|
||||
/* Disable Bus Mastering for this one device */
|
||||
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
||||
reg32 &= ~PCI_COMMAND_MASTER;
|
||||
pci_write_config32(dev, PCI_COMMAND, reg32);
|
||||
|
||||
/* If this is a bridge, then follow it. */
|
||||
hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
|
||||
hdr &= 0x7f;
|
||||
if (hdr == PCI_HEADER_TYPE_BRIDGE ||
|
||||
hdr == PCI_HEADER_TYPE_CARDBUS) {
|
||||
unsigned int buses;
|
||||
buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
|
||||
busmaster_disable_on_bus((buses >> 8) & 0xff);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void southbridge_gate_memory_reset_real(int offset,
|
||||
u16 use, u16 io, u16 lvl)
|
||||
{
|
||||
|
|
@ -334,7 +94,7 @@ static void southbridge_gate_memory_reset_real(int offset,
|
|||
* Intel reference designs all use GPIO 60 but it is
|
||||
* not a requirement and boards could use a different pin.
|
||||
*/
|
||||
static void southbridge_gate_memory_reset(void)
|
||||
void southbridge_gate_memory_reset(void)
|
||||
{
|
||||
u16 gpiobase;
|
||||
|
||||
|
|
@ -354,377 +114,7 @@ static void southbridge_gate_memory_reset(void)
|
|||
gpiobase + GP_LVL);
|
||||
}
|
||||
|
||||
static void xhci_sleep(u8 slp_typ)
|
||||
{
|
||||
u32 reg32, xhci_bar;
|
||||
u16 reg16;
|
||||
|
||||
switch (slp_typ) {
|
||||
case ACPI_S3:
|
||||
case ACPI_S4:
|
||||
reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);
|
||||
reg16 &= ~0x03UL;
|
||||
pci_write_config32(PCH_XHCI_DEV, 0x74, reg16);
|
||||
|
||||
reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND);
|
||||
reg32 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
|
||||
pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32);
|
||||
|
||||
xhci_bar = pci_read_config32(PCH_XHCI_DEV,
|
||||
PCI_BASE_ADDRESS_0) & ~0xFUL;
|
||||
|
||||
if ((xhci_bar + 0x4C0) & 1)
|
||||
pch_iobp_update(0xEC000082, ~0UL, (3 << 2));
|
||||
if ((xhci_bar + 0x4D0) & 1)
|
||||
pch_iobp_update(0xEC000182, ~0UL, (3 << 2));
|
||||
if ((xhci_bar + 0x4E0) & 1)
|
||||
pch_iobp_update(0xEC000282, ~0UL, (3 << 2));
|
||||
if ((xhci_bar + 0x4F0) & 1)
|
||||
pch_iobp_update(0xEC000382, ~0UL, (3 << 2));
|
||||
|
||||
reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND);
|
||||
reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
|
||||
pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32);
|
||||
|
||||
reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);
|
||||
reg16 |= 0x03;
|
||||
pci_write_config16(PCH_XHCI_DEV, 0x74, reg16);
|
||||
break;
|
||||
|
||||
case ACPI_S5:
|
||||
reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);
|
||||
reg16 |= ((1 << 8) | 0x03);
|
||||
pci_write_config16(PCH_XHCI_DEV, 0x74, reg16);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void southbridge_smi_sleep(void)
|
||||
{
|
||||
u8 reg8;
|
||||
u32 reg32;
|
||||
u8 slp_typ;
|
||||
u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
|
||||
|
||||
// save and recover RTC port values
|
||||
u8 tmp70, tmp72;
|
||||
tmp70 = inb(0x70);
|
||||
tmp72 = inb(0x72);
|
||||
get_option(&s5pwr, "power_on_after_fail");
|
||||
outb(tmp70, 0x70);
|
||||
outb(tmp72, 0x72);
|
||||
|
||||
/* First, disable further SMIs */
|
||||
reg8 = inb(pmbase + SMI_EN);
|
||||
reg8 &= ~SLP_SMI_EN;
|
||||
outb(reg8, pmbase + SMI_EN);
|
||||
|
||||
/* Figure out SLP_TYP */
|
||||
reg32 = inl(pmbase + PM1_CNT);
|
||||
printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
|
||||
slp_typ = acpi_sleep_from_pm1(reg32);
|
||||
|
||||
if (smm_get_gnvs()->xhci)
|
||||
xhci_sleep(slp_typ);
|
||||
|
||||
/* Do any mainboard sleep handling */
|
||||
mainboard_smi_sleep(slp_typ);
|
||||
|
||||
#if CONFIG(ELOG_GSMI)
|
||||
/* Log S3, S4, and S5 entry */
|
||||
if (slp_typ >= ACPI_S3)
|
||||
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
|
||||
#endif
|
||||
|
||||
/* Next, do the deed.
|
||||
*/
|
||||
|
||||
switch (slp_typ) {
|
||||
case ACPI_S0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
|
||||
case ACPI_S1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
|
||||
case ACPI_S3:
|
||||
printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
|
||||
|
||||
/* Gate memory reset */
|
||||
southbridge_gate_memory_reset();
|
||||
|
||||
/* Invalidate the cache before going to S3 */
|
||||
wbinvd();
|
||||
break;
|
||||
case ACPI_S4: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
|
||||
case ACPI_S5:
|
||||
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
|
||||
|
||||
outl(0, pmbase + GPE0_EN);
|
||||
|
||||
/* Always set the flag in case CMOS was changed on runtime. For
|
||||
* "KEEP", switch to "OFF" - KEEP is software emulated
|
||||
*/
|
||||
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
|
||||
if (s5pwr == MAINBOARD_POWER_ON) {
|
||||
reg8 &= ~1;
|
||||
} else {
|
||||
reg8 |= 1;
|
||||
}
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
|
||||
|
||||
/* also iterates over all bridges on bus 0 */
|
||||
busmaster_disable_on_bus(0);
|
||||
break;
|
||||
default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
|
||||
}
|
||||
|
||||
/* Write back to the SLP register to cause the originally intended
|
||||
* event again. We need to set BIT13 (SLP_EN) though to make the
|
||||
* sleep happen.
|
||||
*/
|
||||
outl(reg32 | SLP_EN, pmbase + PM1_CNT);
|
||||
|
||||
/* Make sure to stop executing code here for S3/S4/S5 */
|
||||
if (slp_typ >= ACPI_S3)
|
||||
halt();
|
||||
|
||||
/* In most sleep states, the code flow of this function ends at
|
||||
* the line above. However, if we entered sleep state S1 and wake
|
||||
* up again, we will continue to execute code in this function.
|
||||
*/
|
||||
reg32 = inl(pmbase + PM1_CNT);
|
||||
if (reg32 & SCI_EN) {
|
||||
/* The OS is not an ACPI OS, so we set the state to S0 */
|
||||
reg32 &= ~(SLP_EN | SLP_TYP);
|
||||
outl(reg32, pmbase + PM1_CNT);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Look for Synchronous IO SMI and use save state from that
|
||||
* core in case we are not running on the same core that
|
||||
* initiated the IO transaction.
|
||||
*/
|
||||
static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
|
||||
{
|
||||
em64t101_smm_state_save_area_t *state;
|
||||
int node;
|
||||
|
||||
/* Check all nodes looking for the one that issued the IO */
|
||||
for (node = 0; node < CONFIG_MAX_CPUS; node++) {
|
||||
state = smm_get_save_state(node);
|
||||
|
||||
/* Check for Synchronous IO (bit0 == 1) */
|
||||
if (!(state->io_misc_info & (1 << 0)))
|
||||
continue;
|
||||
|
||||
/* Make sure it was a write (bit4 == 0) */
|
||||
if (state->io_misc_info & (1 << 4))
|
||||
continue;
|
||||
|
||||
/* Check for APMC IO port */
|
||||
if (((state->io_misc_info >> 16) & 0xff) != APM_CNT)
|
||||
continue;
|
||||
|
||||
/* Check AX against the requested command */
|
||||
if ((state->rax & 0xff) != cmd)
|
||||
continue;
|
||||
|
||||
return state;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#if CONFIG(ELOG_GSMI)
|
||||
static void southbridge_smi_gsmi(void)
|
||||
{
|
||||
u32 *ret, *param;
|
||||
u8 sub_command;
|
||||
em64t101_smm_state_save_area_t *io_smi =
|
||||
smi_apmc_find_state_save(APM_CNT_ELOG_GSMI);
|
||||
|
||||
if (!io_smi)
|
||||
return;
|
||||
|
||||
/* Command and return value in EAX */
|
||||
ret = (u32*)&io_smi->rax;
|
||||
sub_command = (u8)(*ret >> 8);
|
||||
|
||||
/* Parameter buffer in EBX */
|
||||
param = (u32*)&io_smi->rbx;
|
||||
|
||||
/* drivers/elog/gsmi.c */
|
||||
*ret = gsmi_exec(sub_command, param);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void southbridge_smi_apmc(void)
|
||||
{
|
||||
u32 pmctrl;
|
||||
u8 reg8;
|
||||
em64t101_smm_state_save_area_t *state;
|
||||
|
||||
/* Emulate B2 register as the FADT / Linux expects it */
|
||||
|
||||
reg8 = inb(APM_CNT);
|
||||
switch (reg8) {
|
||||
case APM_CNT_CST_CONTROL:
|
||||
/* Calling this function seems to cause
|
||||
* some kind of race condition in Linux
|
||||
* and causes a kernel oops
|
||||
*/
|
||||
printk(BIOS_DEBUG, "C-state control\n");
|
||||
break;
|
||||
case APM_CNT_PST_CONTROL:
|
||||
/* Calling this function seems to cause
|
||||
* some kind of race condition in Linux
|
||||
* and causes a kernel oops
|
||||
*/
|
||||
printk(BIOS_DEBUG, "P-state control\n");
|
||||
break;
|
||||
case APM_CNT_ACPI_DISABLE:
|
||||
pmctrl = inl(pmbase + PM1_CNT);
|
||||
pmctrl &= ~SCI_EN;
|
||||
outl(pmctrl, pmbase + PM1_CNT);
|
||||
printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
|
||||
break;
|
||||
case APM_CNT_ACPI_ENABLE:
|
||||
pmctrl = inl(pmbase + PM1_CNT);
|
||||
pmctrl |= SCI_EN;
|
||||
outl(pmctrl, pmbase + PM1_CNT);
|
||||
printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
|
||||
break;
|
||||
case APM_CNT_GNVS_UPDATE:
|
||||
if (smm_initialized) {
|
||||
printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
|
||||
return;
|
||||
}
|
||||
state = smi_apmc_find_state_save(reg8);
|
||||
if (state) {
|
||||
/* EBX in the state save contains the GNVS pointer */
|
||||
gnvs = (global_nvs_t *)((u32)state->rbx);
|
||||
smm_initialized = 1;
|
||||
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
|
||||
}
|
||||
break;
|
||||
#if CONFIG(ELOG_GSMI)
|
||||
case APM_CNT_ELOG_GSMI:
|
||||
southbridge_smi_gsmi();
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
|
||||
mainboard_smi_apmc(reg8);
|
||||
}
|
||||
|
||||
static void southbridge_smi_pm1(void)
|
||||
{
|
||||
u16 pm1_sts;
|
||||
|
||||
pm1_sts = reset_pm1_status();
|
||||
dump_pm1_status(pm1_sts);
|
||||
|
||||
/* While OSPM is not active, poweroff immediately
|
||||
* on a power button event.
|
||||
*/
|
||||
if (pm1_sts & PWRBTN_STS) {
|
||||
// power button pressed
|
||||
u32 reg32;
|
||||
reg32 = (7 << 10) | (1 << 13);
|
||||
#if CONFIG(ELOG_GSMI)
|
||||
elog_add_event(ELOG_TYPE_POWER_BUTTON);
|
||||
#endif
|
||||
outl(reg32, pmbase + PM1_CNT);
|
||||
}
|
||||
}
|
||||
|
||||
static void southbridge_smi_gpe0(void)
|
||||
{
|
||||
u32 gpe0_sts;
|
||||
|
||||
gpe0_sts = reset_gpe0_status();
|
||||
dump_gpe0_status(gpe0_sts);
|
||||
}
|
||||
|
||||
static void southbridge_smi_gpi(void)
|
||||
{
|
||||
u16 reg16;
|
||||
reg16 = inw(pmbase + ALT_GP_SMI_STS);
|
||||
outw(reg16, pmbase + ALT_GP_SMI_STS);
|
||||
|
||||
reg16 &= inw(pmbase + ALT_GP_SMI_EN);
|
||||
|
||||
mainboard_smi_gpi(reg16);
|
||||
|
||||
if (reg16)
|
||||
printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);
|
||||
|
||||
outw(reg16, pmbase + ALT_GP_SMI_STS);
|
||||
}
|
||||
|
||||
static void southbridge_smi_mc(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
reg32 = inl(pmbase + SMI_EN);
|
||||
|
||||
/* Are periodic SMIs enabled? */
|
||||
if ((reg32 & MCSMI_EN) == 0)
|
||||
return;
|
||||
|
||||
printk(BIOS_DEBUG, "Microcontroller SMI.\n");
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void southbridge_smi_tco(void)
|
||||
{
|
||||
u32 tco_sts;
|
||||
|
||||
tco_sts = reset_tco_status();
|
||||
|
||||
/* Any TCO event? */
|
||||
if (!tco_sts)
|
||||
return;
|
||||
|
||||
if (tco_sts & (1 << 8)) { // BIOSWR
|
||||
u8 bios_cntl;
|
||||
|
||||
bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
|
||||
|
||||
if (bios_cntl & 1) {
|
||||
/* BWE is RW, so the SMI was caused by a
|
||||
* write to BWE, not by a write to the BIOS
|
||||
*/
|
||||
|
||||
/* This is the place where we notice someone
|
||||
* is trying to tinker with the BIOS. We are
|
||||
* trying to be nice and just ignore it. A more
|
||||
* resolute answer would be to power down the
|
||||
* box.
|
||||
*/
|
||||
printk(BIOS_DEBUG, "Switching back to RO\n");
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
|
||||
} /* No else for now? */
|
||||
} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
|
||||
/* Handle TCO timeout */
|
||||
printk(BIOS_DEBUG, "TCO Timeout.\n");
|
||||
} else {
|
||||
dump_tco_status(tco_sts);
|
||||
}
|
||||
}
|
||||
|
||||
static void southbridge_smi_periodic(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
reg32 = inl(pmbase + SMI_EN);
|
||||
|
||||
/* Are periodic SMIs enabled? */
|
||||
if ((reg32 & PERIODIC_EN) == 0)
|
||||
return;
|
||||
|
||||
printk(BIOS_DEBUG, "Periodic SMI.\n");
|
||||
}
|
||||
|
||||
static void southbridge_smi_monitor(void)
|
||||
void southbridge_smi_monitor(void)
|
||||
{
|
||||
#define IOTRAP(x) (trap_sts & (1 << x))
|
||||
u32 trap_sts, trap_cycle;
|
||||
|
|
@ -778,76 +168,18 @@ static void southbridge_smi_monitor(void)
|
|||
#undef IOTRAP
|
||||
}
|
||||
|
||||
typedef void (*smi_handler_t)(void);
|
||||
|
||||
static smi_handler_t southbridge_smi[32] = {
|
||||
NULL, // [0] reserved
|
||||
NULL, // [1] reserved
|
||||
NULL, // [2] BIOS_STS
|
||||
NULL, // [3] LEGACY_USB_STS
|
||||
southbridge_smi_sleep, // [4] SLP_SMI_STS
|
||||
southbridge_smi_apmc, // [5] APM_STS
|
||||
NULL, // [6] SWSMI_TMR_STS
|
||||
NULL, // [7] reserved
|
||||
southbridge_smi_pm1, // [8] PM1_STS
|
||||
southbridge_smi_gpe0, // [9] GPE0_STS
|
||||
southbridge_smi_gpi, // [10] GPI_STS
|
||||
southbridge_smi_mc, // [11] MCSMI_STS
|
||||
NULL, // [12] DEVMON_STS
|
||||
southbridge_smi_tco, // [13] TCO_STS
|
||||
southbridge_smi_periodic, // [14] PERIODIC_STS
|
||||
NULL, // [15] SERIRQ_SMI_STS
|
||||
NULL, // [16] SMBUS_SMI_STS
|
||||
NULL, // [17] LEGACY_USB2_STS
|
||||
NULL, // [18] INTEL_USB2_STS
|
||||
NULL, // [19] reserved
|
||||
NULL, // [20] PCI_EXP_SMI_STS
|
||||
southbridge_smi_monitor, // [21] MONITOR_STS
|
||||
NULL, // [22] reserved
|
||||
NULL, // [23] reserved
|
||||
NULL, // [24] reserved
|
||||
NULL, // [25] EL_SMI_STS
|
||||
NULL, // [26] SPI_STS
|
||||
NULL, // [27] reserved
|
||||
NULL, // [28] reserved
|
||||
NULL, // [29] reserved
|
||||
NULL, // [30] reserved
|
||||
NULL // [31] reserved
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Interrupt handler for SMI#
|
||||
* @param node
|
||||
* @param state_save
|
||||
*/
|
||||
void southbridge_smi_handler(void)
|
||||
void southbridge_update_gnvs(u8 apm_cnt, int *smm_done)
|
||||
{
|
||||
int i, dump = 0;
|
||||
u32 smi_sts;
|
||||
|
||||
/* Update global variable pmbase */
|
||||
pmbase = lpc_get_pmbase();
|
||||
|
||||
/* We need to clear the SMI status registers, or we won't see what's
|
||||
* happening in the following calls.
|
||||
*/
|
||||
smi_sts = reset_smi_status();
|
||||
|
||||
/* Call SMI sub handler for each of the status bits */
|
||||
for (i = 0; i < 31; i++) {
|
||||
if (smi_sts & (1 << i)) {
|
||||
if (southbridge_smi[i]) {
|
||||
southbridge_smi[i]();
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no "
|
||||
"handler available.\n", i);
|
||||
dump = 1;
|
||||
}
|
||||
}
|
||||
em64t101_smm_state_save_area_t *state =
|
||||
smi_apmc_find_state_save(apm_cnt);
|
||||
if (state) {
|
||||
/* EBX in the state save contains the GNVS pointer */
|
||||
gnvs = (global_nvs_t *)((u32)state->rbx);
|
||||
*smm_done = 1;
|
||||
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
|
||||
}
|
||||
|
||||
if (dump) {
|
||||
dump_smi_status(smi_sts);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void southbridge_finalize_all(void)
|
||||
{
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue