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mb/google/hatch: mushu: Add F75303 temp sensor to dptf 

Update the following in dptf.asl
- Add support for TSR3
- Change TSR0/TSR1/TSR2/TSR3
  From: Charger, 5V,  GPU       , None
  To:   Charger, GPU, F75303_GPU, F75303_GPU_POWER
- Adjust fan/cpu trip point accordingly
- Fix formating in dptf.asl
- Throttle charger when TSR0 (charger) is hot instead of throttle CPU

BUG=b:158676970
BRANCH=None
TEST=grep . /sys/class/thermal/thermal_zone5/{type,temp}
/sys/class/thermal/thermal_zone5/type:TSR3
/sys/class/thermal/thermal_zone5/temp:50800

Change-Id: Iedbb6bc7c1e59a027119c70791b9bc8a4d83ff87
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42270
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Bob Moragues <moragues@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Puthikorn Voravootivat 2020-06-10 15:17:58 -07:00 committed by Patrick Georgi
parent 2fdabd9038
commit 549a853f8f
1 changed files with 46 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

74
src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl
View File

@ -7,10 +7,10 @@
#define DPTF_CPU_ACTIVE_AC2 65 #define DPTF_CPU_ACTIVE_AC2 65
#define DPTF_CPU_ACTIVE_AC3 60 #define DPTF_CPU_ACTIVE_AC3 60
#define DPTF_CPU_ACTIVE_AC4 50 #define DPTF_CPU_ACTIVE_AC4 50
#define DPTF_CPU_ACTIVE_AC5 40 #define DPTF_CPU_ACTIVE_AC5 40
#define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_ID 0
#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" #define DPTF_TSR0_SENSOR_NAME "Charger"
#define DPTF_TSR0_PASSIVE 90 #define DPTF_TSR0_PASSIVE 90
#define DPTF_TSR0_CRITICAL 99 #define DPTF_TSR0_CRITICAL 99
#define DPTF_TSR0_ACTIVE_AC0 80 #define DPTF_TSR0_ACTIVE_AC0 80
@ -18,29 +18,40 @@
#define DPTF_TSR0_ACTIVE_AC2 65 #define DPTF_TSR0_ACTIVE_AC2 65
#define DPTF_TSR0_ACTIVE_AC3 60 #define DPTF_TSR0_ACTIVE_AC3 60
#define DPTF_TSR0_ACTIVE_AC4 55 #define DPTF_TSR0_ACTIVE_AC4 55
#define DPTF_TSR0_ACTIVE_AC5 50 #define DPTF_TSR0_ACTIVE_AC5 50
#define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_ID 2
#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" #define DPTF_TSR1_SENSOR_NAME "GPU"
#define DPTF_TSR1_PASSIVE 90 #define DPTF_TSR1_PASSIVE 93
#define DPTF_TSR1_CRITICAL 99 #define DPTF_TSR1_CRITICAL 99
#define DPTF_TSR1_ACTIVE_AC0 80 #define DPTF_TSR1_ACTIVE_AC0 85
#define DPTF_TSR1_ACTIVE_AC1 70 #define DPTF_TSR1_ACTIVE_AC1 70
#define DPTF_TSR1_ACTIVE_AC2 65 #define DPTF_TSR1_ACTIVE_AC2 65
#define DPTF_TSR1_ACTIVE_AC3 60 #define DPTF_TSR1_ACTIVE_AC3 60
#define DPTF_TSR1_ACTIVE_AC4 55 #define DPTF_TSR1_ACTIVE_AC4 50
#define DPTF_TSR1_ACTIVE_AC5 50 #define DPTF_TSR1_ACTIVE_AC5 40
#define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_ID 4
#define DPTF_TSR2_SENSOR_NAME "dGPU" #define DPTF_TSR2_SENSOR_NAME "F75303_GPU"
#define DPTF_TSR2_PASSIVE 93 #define DPTF_TSR2_PASSIVE 93
#define DPTF_TSR2_CRITICAL 99 #define DPTF_TSR2_CRITICAL 99
#define DPTF_TSR2_ACTIVE_AC0 85 #define DPTF_TSR2_ACTIVE_AC0 85
#define DPTF_TSR2_ACTIVE_AC1 70 #define DPTF_TSR2_ACTIVE_AC1 70
#define DPTF_TSR2_ACTIVE_AC2 65 #define DPTF_TSR2_ACTIVE_AC2 65
#define DPTF_TSR2_ACTIVE_AC3 60 #define DPTF_TSR2_ACTIVE_AC3 60
#define DPTF_TSR2_ACTIVE_AC4 50 #define DPTF_TSR2_ACTIVE_AC4 50
#define DPTF_TSR2_ACTIVE_AC5 40 #define DPTF_TSR2_ACTIVE_AC5 40
#define DPTF_TSR3_SENSOR_ID 5
#define DPTF_TSR3_SENSOR_NAME "F75303_GPU_POWER"
#define DPTF_TSR3_PASSIVE 90
#define DPTF_TSR3_CRITICAL 99
#define DPTF_TSR3_ACTIVE_AC0 80
#define DPTF_TSR3_ACTIVE_AC1 70
#define DPTF_TSR3_ACTIVE_AC2 65
#define DPTF_TSR3_ACTIVE_AC3 60
#define DPTF_TSR3_ACTIVE_AC4 55
#define DPTF_TSR3_ACTIVE_AC5 50
#define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_CHARGER
#define DPTF_ENABLE_FAN_CONTROL #define DPTF_ENABLE_FAN_CONTROL
@ -93,23 +104,30 @@ Name (DART, Package () {
0, 0, 0 0, 0, 0
}, },
Package () { Package () {
\_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 77, 71, 68, 65, 59, 55, 0, \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 77, 71, 68, 65, 59, 55, 0,
0, 0, 0 0, 0, 0
} },
Package () {
\_SB.DPTF.TFN1, \_SB.DPTF.TSR3, 100, 77, 71, 68, 65, 59, 55, 0,
0, 0, 0
}
}) })
Name (DTRT, Package () { Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */ /* CPU Throttle Effect on CPU */
Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 }, Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 },
/* CPU Throttle Effect on TSR0 */ /* CPU Throttle Effect on GPU (TSR1) */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 10, 0, 0, 0, 0 },
/* CPU Throttle Effect on TSR1 */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 10, 0, 0, 0, 0 }, Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 10, 0, 0, 0, 0 },
/* CPU Throttle Effect on dGPU (TSR2) */ /* CPU Throttle Effect on F75303_GPU (TSR2) */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 10, 0, 0, 0, 0 }, Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 10, 0, 0, 0, 0 },
/* CPU Throttle Effect on F75303_GPU_POWER (TSR3) */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 10, 0, 0, 0, 0 },
/* Charger Throttle Effect on Charger (TSR0) */
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 10, 0, 0, 0, 0 }
}) })
Name (MPPC, Package () Name (MPPC, Package ()