diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 34f760ff42..ae202456a0 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -143,7 +143,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 
 static unsigned long soc_fill_dmar(unsigned long current)
 {
-	struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
 	uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
 	uint64_t defvtbar = MCHBAR64(DEFVTBAR) & VTBAR_MASK;
 	bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
@@ -151,7 +150,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
 	unsigned long tmp;
 
 	/* IGD has to be enabled, GFXVTBAR set and enabled. */
-	const bool emit_igd = is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten;
+	const bool emit_igd = is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten;
 
 	/* First, add DRHD entries */
 	if (emit_igd) {
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 7172231c07..9694c67fc6 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -533,7 +533,6 @@ static void glk_fsp_silicon_init_params_cb(
 {
 #if CONFIG(SOC_INTEL_GEMINILAKE)
 	uint8_t port;
-	struct device *dev;
 
 	for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
 		if (!cfg->usb2eye[port].Usb20OverrideEn)
@@ -549,8 +548,7 @@ static void glk_fsp_silicon_init_params_cb(
 			cfg->usb2eye[port].Usb20IUsbTxEmphasisEn;
 	}
 
-	dev = pcidev_path_on_root(SA_GLK_DEVFN_GMM);
-	silconfig->Gmm = is_dev_enabled(dev);
+	silconfig->Gmm = is_devfn_enabled(SA_GLK_DEVFN_GMM);
 
 	/* On Geminilake, we need to override the default FSP PCIe de-emphasis
 	 * settings using the device tree settings. This is because PCIe
@@ -693,8 +691,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 	/* Set VTD feature according to devicetree */
 	silconfig->VtdEnable = cfg->enable_vtd;
 
-	dev = pcidev_path_on_root(SA_DEVFN_IGD);
-	silconfig->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev);
+	silconfig->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
 
 	silconfig->PavpEnable = CONFIG(PAVP);
 
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 0aa6c397e3..13a55dc3b5 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -256,12 +256,10 @@ static void soc_memory_init_params(FSPM_UPD *mupd)
 
 static void parse_devicetree_setting(FSPM_UPD *m_upd)
 {
-	DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_NPK);
-
 #if CONFIG(SOC_INTEL_GEMINILAKE)
-	m_upd->FspmConfig.TraceHubEn = is_dev_enabled(dev);
+	m_upd->FspmConfig.TraceHubEn = is_devfn_enabled(PCH_DEVFN_NPK);
 #else
-	m_upd->FspmConfig.NpkEn = is_dev_enabled(dev);
+	m_upd->FspmConfig.NpkEn = is_devfn_enabled(PCH_DEVFN_NPK);
 #endif
 }