mb/google/brya: Enable Fast VMode for brya0, skolas and skolas4es
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP threshold. FSP silicon discards the request if the Voltage Regulator or SoC does not support the feature. BUG🅱️259057787 TEST:Verify that the feature is enabled by reading from pcode No PnP regression observed BRANCH=firmware-brya-14505.B Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I7e318534f1429af8ec06048430966344ddd346a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69579 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Jeremy Compostella <jeremy.compostella@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -44,6 +44,10 @@ fw_config
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end
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end
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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register "domain_vr_config[VR_DOMAIN_IA]" = "{
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.enable_fast_vmode = 1,
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}"
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register "sagv" = "SaGv_Enabled"
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register "sagv" = "SaGv_Enabled"
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register "platform_pmax" = "145"
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register "platform_pmax" = "145"
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@ -44,6 +44,10 @@ fw_config
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end
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end
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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register "domain_vr_config[VR_DOMAIN_IA]" = "{
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.enable_fast_vmode = 1,
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}"
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register "sagv" = "SaGv_Enabled"
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register "sagv" = "SaGv_Enabled"
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register "platform_pmax" = "145"
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register "platform_pmax" = "145"
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@ -40,6 +40,10 @@ fw_config
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end
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end
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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register "domain_vr_config[VR_DOMAIN_IA]" = "{
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.enable_fast_vmode = 1,
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}"
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register "sagv" = "SaGv_Enabled"
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register "sagv" = "SaGv_Enabled"
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register "platform_pmax" = "145"
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register "platform_pmax" = "145"
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