mb/google/brya: Enable Fast VMode for brya0, skolas and skolas4es

Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP
threshold.

FSP silicon discards the request if the Voltage Regulator or SoC does
not support the feature.

BUG🅱️259057787
TEST:Verify that the feature is enabled by reading from pcode
     No PnP regression observed
BRANCH=firmware-brya-14505.B

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I7e318534f1429af8ec06048430966344ddd346a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69579
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Jeremy Compostella <jeremy.compostella@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jeremy Compostella 2022-11-14 10:28:27 -08:00 committed by Nick Vaccaro
parent fade723b25
commit 54a6b1f281
3 changed files with 12 additions and 0 deletions

View File

@ -44,6 +44,10 @@ fw_config
end
chip soc/intel/alderlake
register "domain_vr_config[VR_DOMAIN_IA]" = "{
.enable_fast_vmode = 1,
}"
register "sagv" = "SaGv_Enabled"
register "platform_pmax" = "145"

View File

@ -44,6 +44,10 @@ fw_config
end
chip soc/intel/alderlake
register "domain_vr_config[VR_DOMAIN_IA]" = "{
.enable_fast_vmode = 1,
}"
register "sagv" = "SaGv_Enabled"
register "platform_pmax" = "145"

View File

@ -40,6 +40,10 @@ fw_config
end
chip soc/intel/alderlake
register "domain_vr_config[VR_DOMAIN_IA]" = "{
.enable_fast_vmode = 1,
}"
register "sagv" = "SaGv_Enabled"
register "platform_pmax" = "145"