soc/intel/xeon_sp: Add read CPU PPIN MSR function
These changes are in accordance with the documentation: [*] page 208-209 Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual, Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US Tested on OCP Tioga Pass and Delta Lake. Change-Id: I8c2eac055a065c06859a3cb7b48ed59f15ae2fc4 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42901 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -188,3 +188,34 @@ void cpx_init_cpus(struct device *dev)
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/* update numa domain for all cpu devices */
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xeonsp_init_cpu_config();
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}
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msr_t read_msr_ppin(void)
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{
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msr_t ppin = {0};
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msr_t msr;
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/* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */
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msr = rdmsr(MSR_PLATFORM_INFO);
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if ((msr.lo & MSR_PPIN_CAP) == 0) {
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printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n");
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return ppin;
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}
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/* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */
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msr = rdmsr(MSR_PPIN_CTL);
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if (msr.lo & MSR_PPIN_CTL_LOCK) {
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printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n");
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return ppin;
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}
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if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) {
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/* Set MSR_PPIN_CTL ENABLE to 1 */
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msr.lo |= MSR_PPIN_CTL_ENABLE;
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wrmsr(MSR_PPIN_CTL, msr);
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}
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ppin = rdmsr(MSR_PPIN);
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/* Set enable to 0 after reading MSR_PPIN */
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msr.lo &= ~MSR_PPIN_CTL_ENABLE;
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wrmsr(MSR_PPIN_CTL, msr);
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return ppin;
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}
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@ -4,6 +4,7 @@
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#define _SOC_CPU_H
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#include <device/device.h>
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#include <cpu/x86/msr.h>
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#define CPUID_COOPERLAKE_SP_A0 0x05065a
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@ -11,5 +12,6 @@
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#define CPU_BCLK 100
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void cpx_init_cpus(struct device *dev);
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msr_t read_msr_ppin(void);
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#endif
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@ -244,3 +244,34 @@ void xeon_sp_init_cpus(struct device *dev)
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FUNC_EXIT();
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}
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msr_t read_msr_ppin(void)
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{
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msr_t ppin = {0};
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msr_t msr;
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/* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */
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msr = rdmsr(MSR_PLATFORM_INFO);
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if ((msr.lo & MSR_PPIN_CAP) == 0) {
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printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n");
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return ppin;
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}
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/* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */
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msr = rdmsr(MSR_PPIN_CTL);
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if (msr.lo & MSR_PPIN_CTL_LOCK) {
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printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n");
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return ppin;
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}
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if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) {
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/* Set MSR_PPIN_CTL ENABLE to 1 */
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msr.lo |= MSR_PPIN_CTL_ENABLE;
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wrmsr(MSR_PPIN_CTL, msr);
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}
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ppin = rdmsr(MSR_PPIN);
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/* Set enable to 0 after reading MSR_PPIN */
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msr.lo &= ~MSR_PPIN_CTL_ENABLE;
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wrmsr(MSR_PPIN_CTL, msr);
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return ppin;
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}
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@ -4,6 +4,7 @@
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#define _SOC_CPU_H_
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#include <device/device.h>
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#include <cpu/x86/msr.h>
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/* SKXSP CPUID */
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#define CPUID_SKYLAKE_SP_A0_A1 0x506f0
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@ -15,5 +16,6 @@
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int get_cpu_count(void);
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void xeon_sp_init_cpus(struct device *dev);
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msr_t read_msr_ppin(void);
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#endif
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