soc/intel/xeon_sp: Add read CPU PPIN MSR function

These changes are in accordance with the documentation:
[*] page 208-209
    Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
    Volume 4: Model-Specific Registers. May 2019.
    Order Number: 335592-070US

Tested on OCP Tioga Pass and Delta Lake.

Change-Id: I8c2eac055a065c06859a3cb7b48ed59f15ae2fc4
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42901
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Johnny Lin 2020-06-30 11:29:56 +08:00 committed by Philipp Deppenwiese
parent 99198b2f76
commit 54a7f41de1
4 changed files with 66 additions and 0 deletions

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@ -188,3 +188,34 @@ void cpx_init_cpus(struct device *dev)
/* update numa domain for all cpu devices */
xeonsp_init_cpu_config();
}
msr_t read_msr_ppin(void)
{
msr_t ppin = {0};
msr_t msr;
/* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */
msr = rdmsr(MSR_PLATFORM_INFO);
if ((msr.lo & MSR_PPIN_CAP) == 0) {
printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n");
return ppin;
}
/* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */
msr = rdmsr(MSR_PPIN_CTL);
if (msr.lo & MSR_PPIN_CTL_LOCK) {
printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n");
return ppin;
}
if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) {
/* Set MSR_PPIN_CTL ENABLE to 1 */
msr.lo |= MSR_PPIN_CTL_ENABLE;
wrmsr(MSR_PPIN_CTL, msr);
}
ppin = rdmsr(MSR_PPIN);
/* Set enable to 0 after reading MSR_PPIN */
msr.lo &= ~MSR_PPIN_CTL_ENABLE;
wrmsr(MSR_PPIN_CTL, msr);
return ppin;
}

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@ -4,6 +4,7 @@
#define _SOC_CPU_H
#include <device/device.h>
#include <cpu/x86/msr.h>
#define CPUID_COOPERLAKE_SP_A0 0x05065a
@ -11,5 +12,6 @@
#define CPU_BCLK 100
void cpx_init_cpus(struct device *dev);
msr_t read_msr_ppin(void);
#endif

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@ -244,3 +244,34 @@ void xeon_sp_init_cpus(struct device *dev)
FUNC_EXIT();
}
msr_t read_msr_ppin(void)
{
msr_t ppin = {0};
msr_t msr;
/* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */
msr = rdmsr(MSR_PLATFORM_INFO);
if ((msr.lo & MSR_PPIN_CAP) == 0) {
printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n");
return ppin;
}
/* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */
msr = rdmsr(MSR_PPIN_CTL);
if (msr.lo & MSR_PPIN_CTL_LOCK) {
printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n");
return ppin;
}
if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) {
/* Set MSR_PPIN_CTL ENABLE to 1 */
msr.lo |= MSR_PPIN_CTL_ENABLE;
wrmsr(MSR_PPIN_CTL, msr);
}
ppin = rdmsr(MSR_PPIN);
/* Set enable to 0 after reading MSR_PPIN */
msr.lo &= ~MSR_PPIN_CTL_ENABLE;
wrmsr(MSR_PPIN_CTL, msr);
return ppin;
}

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@ -4,6 +4,7 @@
#define _SOC_CPU_H_
#include <device/device.h>
#include <cpu/x86/msr.h>
/* SKXSP CPUID */
#define CPUID_SKYLAKE_SP_A0_A1 0x506f0
@ -15,5 +16,6 @@
int get_cpu_count(void);
void xeon_sp_init_cpus(struct device *dev);
msr_t read_msr_ppin(void);
#endif