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soc/intel/broadwell: Drop unnecessary `sa_dev` 

Change-Id: Icc70adb0c3527a082622fd0ab70888e6cdf6b0ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46982
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-29 20:36:47 +01:00 committed by Hung-Te Lin
parent dc873cc0c6
commit 54b5e20cf8
1 changed files with 1 additions and 2 deletions
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3
src/soc/intel/broadwell/northbridge.c
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@ -280,7 +280,6 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
uint64_t mc_values[NUM_MAP_ENTRIES]; uint64_t mc_values[NUM_MAP_ENTRIES];
unsigned long dpr_size = 0; unsigned long dpr_size = 0;
u32 dpr_reg; u32 dpr_reg;
struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
/* Read in the MAP registers and report their values. */ /* Read in the MAP registers and report their values. */
mc_read_map_entries(dev, &mc_values[0]); mc_read_map_entries(dev, &mc_values[0]);
@ -292,7 +291,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
* the DPR register reports the TOP of the region, which is the same * the DPR register reports the TOP of the region, which is the same
* as TSEG base. The region size is reported in MiB in bits 11:4. * as TSEG base. The region size is reported in MiB in bits 11:4.
*/ */
dpr_reg = pci_read_config32(sa_dev, DPR); dpr_reg = pci_read_config32(dev, DPR);
if (dpr_reg & DPR_EPM) { if (dpr_reg & DPR_EPM) {
dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16; dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16;
printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size); printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size);