From 54c80e1df16d356dc73030903daece5fcb50e7bc Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 21 Feb 2023 17:59:42 +0100 Subject: [PATCH] soc/amd/*/acpi: add comment about p_lvl[2,3]_lat FADT field usage The latency values in the _CST package override the values in the p_lvl2_lat and p_lvl3_lat FADT fields. In Picasso, Cezanne, Mendocino, Phoenix and Glinda generate_cpu_entries generates the _CST packages for each CPU device. The coreboot code for Stoneyridge doesn't generate _CST packages for the CPU objects, but those are provided via the PSTATE SSDT binaryPI generates and agesa_write_acpi_tables gets and adds to the ACPI tables. The AGESA reference code also sets those two FADT entries to the equivalents of ACPI_FADT_C2_NOT_SUPPORTED and ACPI_FADT_C3_NOT_SUPPORTED so this also matches the AGESA behavior. From the ACPI 6.4 spec: "Values provided by the _CST object override P_LVLx values in P_BLK and P_LVLx_LAT values in the FADT." Signed-off-by: Felix Held Change-Id: I1116a3013576b18b6f521604d6b0a9d75b971e0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73231 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/cezanne/acpi.c | 2 ++ src/soc/amd/glinda/acpi.c | 2 ++ src/soc/amd/mendocino/acpi.c | 2 ++ src/soc/amd/phoenix/acpi.c | 2 ++ src/soc/amd/picasso/acpi.c | 2 ++ src/soc/amd/stoneyridge/acpi.c | 2 ++ 6 files changed, 12 insertions(+) diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index edf20c9b6f..631f388fdf 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -76,6 +76,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fill_fadt_extended_pm_regs(fadt); + /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are + overridden by the _CST packages in the processor devices. */ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 0; /* Not supported */ diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 8d6c008a96..31723b1b4f 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -79,6 +79,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fill_fadt_extended_pm_regs(fadt); + /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are + overridden by the _CST packages in the processor devices. */ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 0; /* Not supported */ diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 6b20b023d5..044b345df1 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -78,6 +78,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fill_fadt_extended_pm_regs(fadt); + /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are + overridden by the _CST packages in the processor devices. */ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 0; /* Not supported */ diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 32dde83651..09c4a15401 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -79,6 +79,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fill_fadt_extended_pm_regs(fadt); + /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are + overridden by the _CST packages in the processor devices. */ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 0; /* Not supported */ diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 1d5a275d42..f6fb9f259d 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -82,6 +82,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fill_fadt_extended_pm_regs(fadt); + /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are + overridden by the _CST packages in the processor devices. */ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index e2fb2e344f..3b45a5ff99 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -74,6 +74,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fill_fadt_extended_pm_regs(fadt); + /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are + overridden by the _CST packages in the PSTATE SSDT. */ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */