cpu/intel/slot_1: Switch to different CAR setup
This moves CAR stack under variable MTRRs and removes old CAR code that used complex fixed MTRRs and placed stack in low memory. Change-Id: I75ec842ae3b6771cc3f7ff652adbe386c03b9a5f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/26586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki
parent
82112b22a2
commit
54d6a288df
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@ -1,238 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2000, 2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2005 Eswar Nallusamy, LANL
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* Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
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* Copyright (C) 2007-2010 coresystems GmbH
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* Copyright (C) 2007 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/lapic_def.h>
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#include <cpu/x86/post_code.h>
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/* Save the BIST result. */
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movl %eax, %ebp
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CacheAsRam:
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/* Set the default memory type and enable fixed and variable MTRRs. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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xorl %edx, %edx
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movl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax
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wrmsr
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/* Clear all MTRRs. */
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xorl %edx, %edx
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movl $all_mtrr_msrs, %esi
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clear_fixed_var_mtrr:
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lodsl (%esi), %eax
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testl %eax, %eax
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jz clear_fixed_var_mtrr_out
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movl %eax, %ecx
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xorl %eax, %eax
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wrmsr
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jmp clear_fixed_var_mtrr
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all_mtrr_msrs:
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/* fixed MTRR MSRs */
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.long MTRR_FIX_64K_00000
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.long MTRR_FIX_16K_80000
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.long MTRR_FIX_16K_A0000
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.long MTRR_FIX_4K_C0000
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.long MTRR_FIX_4K_C8000
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.long MTRR_FIX_4K_D0000
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.long MTRR_FIX_4K_D8000
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.long MTRR_FIX_4K_E0000
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.long MTRR_FIX_4K_E8000
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.long MTRR_FIX_4K_F0000
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.long MTRR_FIX_4K_F8000
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/* var MTRR MSRs */
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.long MTRR_PHYS_BASE(0)
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.long MTRR_PHYS_MASK(0)
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.long MTRR_PHYS_BASE(1)
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.long MTRR_PHYS_MASK(1)
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.long MTRR_PHYS_BASE(2)
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.long MTRR_PHYS_MASK(2)
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.long MTRR_PHYS_BASE(3)
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.long MTRR_PHYS_MASK(3)
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.long MTRR_PHYS_BASE(4)
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.long MTRR_PHYS_MASK(4)
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.long MTRR_PHYS_BASE(5)
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.long MTRR_PHYS_MASK(5)
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.long MTRR_PHYS_BASE(6)
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.long MTRR_PHYS_MASK(6)
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.long MTRR_PHYS_BASE(7)
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.long MTRR_PHYS_MASK(7)
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.long 0x000 /* NULL, end of table */
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clear_fixed_var_mtrr_out:
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/*
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* 0x06 is the WB IO type for a given 4k segment.
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* segs is the number of 4k segments in the area of the particular
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* register we want to use for CAR.
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* reg is the register where the IO type should be stored.
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*/
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.macro extractmask segs, reg
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.if \segs <= 0
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/*
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* The xorl here is superfluous because at the point of first execution
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* of this macro, %eax and %edx are cleared. Later invocations of this
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* macro will have a monotonically increasing segs parameter.
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*/
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xorl \reg, \reg
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.elseif \segs == 1
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movl $0x06000000, \reg /* WB IO type */
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.elseif \segs == 2
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movl $0x06060000, \reg /* WB IO type */
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.elseif \segs == 3
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movl $0x06060600, \reg /* WB IO type */
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.elseif \segs >= 4
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movl $0x06060606, \reg /* WB IO type */
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.endif
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.endm
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/*
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* carsize is the cache size in bytes we want to use for CAR.
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* windowoffset is the 32k-aligned window into CAR size.
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*/
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.macro simplemask carsize, windowoffset
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.set gas_bug_workaround,(((\carsize - \windowoffset) >> 12) - 4)
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extractmask gas_bug_workaround, %eax
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.set gas_bug_workaround,(((\carsize - \windowoffset) >> 12))
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extractmask gas_bug_workaround, %edx
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/*
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* Without the gas bug workaround, the entire macro would consist
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* only of the two lines below:
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* extractmask (((\carsize - \windowoffset) >> 12) - 4), %eax
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* extractmask (((\carsize - \windowoffset) >> 12)), %edx
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*/
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.endm
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#if CONFIG_DCACHE_RAM_SIZE > 0x10000
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#error Invalid CAR size, must be at most 64k.
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#endif
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#if CONFIG_DCACHE_RAM_SIZE < 0x1000
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#error Invalid CAR size, must be at least 4k. This is a processor limitation.
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#endif
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#if (CONFIG_DCACHE_RAM_SIZE & (0x1000 - 1))
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#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
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#endif
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#if CONFIG_DCACHE_RAM_SIZE > 0x8000
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/* Enable caching for 32K-64K using fixed MTRR. */
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movl $MTRR_FIX_4K_C0000, %ecx
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simplemask CONFIG_DCACHE_RAM_SIZE, 0x8000
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wrmsr
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#endif
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/* Enable caching for 0-32K using fixed MTRR. */
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movl $MTRR_FIX_4K_C8000, %ecx
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simplemask CONFIG_DCACHE_RAM_SIZE, 0
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wrmsr
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/* Enable cache for our code in Flash because we do XIP here. */
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movl $MTRR_PHYS_BASE(1), %ecx
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xorl %edx, %edx
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/*
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* IMPORTANT: The following calculation _must_ be done at runtime. See
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* https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
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*/
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movl $copy_and_run, %eax
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andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
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orl $MTRR_TYPE_WRPROT, %eax
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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movl $0x0000000f, %edx
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movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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wrmsr
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/* Enable cache. */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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movl %eax, %cr0
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/* Read the CAR region. This will also fill up the cache.
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* IMPORTANT: This step is mandatory.
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*/
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movl $CONFIG_DCACHE_RAM_BASE, %esi
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cld
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movl $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx
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rep lodsl
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/* Clear the CAR region. */
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movl $CONFIG_DCACHE_RAM_BASE, %edi
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movl $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx
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xorl %eax, %eax
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rep stosl
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movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
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movl %eax, %esp
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lout:
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/* Restore the BIST result. */
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movl %ebp, %eax
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pushl %eax /* BIST */
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call romstage_main
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/* Setup stack as indicated by return value from romstage_main(). */
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movl %eax, %esp
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/* We don't need CAR from now on. */
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/* Disable cache. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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/* Clear the fixed MTRR we used. */
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movl $MTRR_FIX_4K_C8000, %ecx
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xorl %edx, %edx
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xorl %eax, %eax
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wrmsr
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#if CONFIG_DCACHE_RAM_SIZE > 0x8000
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movl $MTRR_FIX_4K_C0000, %ecx
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wrmsr
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#endif
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/*
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* Enable variable and disable fixed MTRRs.
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* Default memory type will be UC.
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*/
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movl $MTRR_DEF_TYPE_MSR, %ecx
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xorl %edx, %edx
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movl $MTRR_DEF_TYPE_EN, %eax
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wrmsr
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/* Enable cache. */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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movl %eax, %cr0
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__main:
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post_code(POST_PREPARE_RAMSTAGE)
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cld /* Clear direction flag. */
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call copy_and_run
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.Lhlt:
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post_code(POST_DEAD_CODE)
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hlt
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jmp .Lhlt
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@ -19,11 +19,6 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/post_code.h>
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#include <cpu/x86/lapic_def.h>
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/* Macro to access Local APIC registers at default base. */
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#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
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#define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff)
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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@ -34,14 +29,7 @@
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cache_as_ram:
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post_code(0x20)
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movl $LAPIC_BASE_MSR, %ecx
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rdmsr
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andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax
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jz ap_init
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/* Zero out all fixed range and variable range MTRRs.
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* For hyper-threaded CPUs these are shared.
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*/
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/* Zero out all fixed range and variable range MTRRs. */
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movl $mtrr_table, %esi
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movl $((mtrr_table_end - mtrr_table) >> 1), %edi
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xorl %eax, %eax
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@ -64,22 +52,7 @@ clear_mtrrs:
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post_code(0x22)
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/* Determine CPU_ADDR_BITS and load PHYSMASK high
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* word to %edx.
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*/
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movl $0x80000000, %eax
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cpuid
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cmpl $0x80000008, %eax
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jc addrsize_no_MSR
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movl $0x80000008, %eax
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cpuid
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movb %al, %cl
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sub $32, %cl
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movl $1, %edx
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shl %cl, %edx
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subl $1, %edx
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jmp addrsize_set_high
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addrsize_no_MSR:
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/* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */
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movl $1, %eax
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cpuid
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andl $(1 << 6 | 1 << 17), %edx /* PAE or PSE36 */
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@ -87,141 +60,13 @@ addrsize_no_MSR:
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movl $0x0f, %edx
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/* Preload high word of address mask (in %edx) for Variable
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* MTRRs 0 and 1 and enable local APIC at default base.
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*/
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MTRRs 0 and 1. */
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addrsize_set_high:
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xorl %eax, %eax
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movl $MTRR_PHYS_MASK(0), %ecx
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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wrmsr
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movl $LAPIC_BASE_MSR, %ecx
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not %edx
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movl %edx, %ebx
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rdmsr
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andl %ebx, %edx
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andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax
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orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax
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wrmsr
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bsp_init:
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post_code(0x23)
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/* Send INIT IPI to all excluding ourself. */
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movl LAPIC(ICR), %edi
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movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax
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1: movl %eax, (%edi)
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movl $0x30, %ecx
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2: pause
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dec %ecx
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jnz 2b
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movl (%edi), %ecx
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andl $LAPIC_ICR_BUSY, %ecx
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jnz 1b
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post_code(0x24)
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movl $1, %eax
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cpuid
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btl $28, %edx
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jnc sipi_complete
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bswapl %ebx
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movzx %bh, %edi
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cmpb $1, %bh
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jbe sipi_complete /* only one LAPIC ID in package */
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movl $0, %eax
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cpuid
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movb $1, %bl
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cmpl $4, %eax
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jb cores_counted
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movl $4, %eax
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movl $0, %ecx
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cpuid
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shr $26, %eax
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movb %al, %bl
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inc %bl
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cores_counted:
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movl %edi, %eax
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divb %bl
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cmpb $1, %al
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jbe sipi_complete /* only LAPIC ID of a core */
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/* For a hyper-threading processor, cache must not be disabled
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* on an AP on the same physical package with the BSP.
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*/
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hyper_threading_cpu:
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/* delay 10 ms */
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movl $10000, %ecx
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1: inb $0x80, %al
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dec %ecx
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jnz 1b
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post_code(0x25)
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/* Send Start IPI to all excluding ourself. */
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movl LAPIC(ICR), %edi
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movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax
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1: movl %eax, (%edi)
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movl $0x30, %ecx
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2: pause
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dec %ecx
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jnz 2b
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movl (%edi), %ecx
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andl $LAPIC_ICR_BUSY, %ecx
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jnz 1b
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/* delay 250 us */
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movl $250, %ecx
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1: inb $0x80, %al
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dec %ecx
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jnz 1b
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post_code(0x26)
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/* Wait for sibling CPU to start. */
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1: movl $(MTRR_PHYS_BASE(0)), %ecx
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rdmsr
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andl %eax, %eax
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jnz sipi_complete
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movl $0x30, %ecx
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2: pause
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dec %ecx
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jnz 2b
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jmp 1b
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ap_init:
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post_code(0x27)
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/* Do not disable cache (so BSP can enable it). */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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movl %eax, %cr0
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post_code(0x28)
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/* MTRR registers are shared between HT siblings. */
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movl $(MTRR_PHYS_BASE(0)), %ecx
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movl $(1 << 12), %eax
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xorl %edx, %edx
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wrmsr
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post_code(0x29)
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ap_halt:
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cli
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1: hlt
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jmp 1b
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sipi_complete:
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post_code(0x2a)
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@ -245,41 +90,6 @@ sipi_complete:
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orl $MTRR_DEF_TYPE_EN, %eax
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wrmsr
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/* Enable L2 cache Write-Back (WBINVD and FLUSH#).
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*
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* MSR is set when DisplayFamily_DisplayModel is one of:
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* 06_0x, 06_17, 06_1C
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*
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* Description says this bit enables use of WBINVD and FLUSH#.
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* Should this be set only after the system bus and/or memory
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* controller can successfully handle write cycles?
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*/
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#define EAX_FAMILY(a) (a << 8) /* for family <= 0fH */
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#define EAX_MODEL(a) (((a & 0xf0) << 12) | ((a & 0xf) << 4))
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movl $1, %eax
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cpuid
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movl %eax, %ebx
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andl $EAX_FAMILY(0x0f), %eax
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cmpl $EAX_FAMILY(0x06), %eax
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jne no_msr_11e
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movl %ebx, %eax
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andl $EAX_MODEL(0xff), %eax
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cmpl $EAX_MODEL(0x17), %eax
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je has_msr_11e
|
||||
cmpl $EAX_MODEL(0x1c), %eax
|
||||
je has_msr_11e
|
||||
andl $EAX_MODEL(0xf0), %eax
|
||||
cmpl $EAX_MODEL(0x00), %eax
|
||||
jne no_msr_11e
|
||||
has_msr_11e:
|
||||
movl $0x11e, %ecx
|
||||
rdmsr
|
||||
orl $(1 << 8), %eax
|
||||
wrmsr
|
||||
no_msr_11e:
|
||||
|
||||
post_code(0x2c)
|
||||
|
||||
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
|
||||
|
|
@ -288,11 +98,16 @@ no_msr_11e:
|
|||
invd
|
||||
movl %eax, %cr0
|
||||
|
||||
/* Clear the cache memory region. This will also fill up the cache. */
|
||||
/* Read then clear the CAR region. This will also fill up the cache.
|
||||
* IMPORTANT: The read is mandatory.
|
||||
*/
|
||||
movl $CACHE_AS_RAM_BASE, %esi
|
||||
movl %esi, %edi
|
||||
cld
|
||||
xorl %eax, %eax
|
||||
movl $CACHE_AS_RAM_BASE, %edi
|
||||
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
|
||||
rep lodsl
|
||||
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
|
||||
xorl %eax, %eax
|
||||
rep stosl
|
||||
|
||||
post_code(0x2d)
|
||||
|
|
|
|||
|
|
@ -1,20 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <cpu/intel/romstage.h>
|
||||
|
||||
asmlinkage void *romstage_main(unsigned long bist)
|
||||
{
|
||||
mainboard_romstage_entry(bist);
|
||||
return (void *)CONFIG_RAMTOP;
|
||||
}
|
||||
|
|
@ -28,7 +28,7 @@ config SLOT_SPECIFIC_OPTIONS # dummy
|
|||
|
||||
config DCACHE_RAM_BASE
|
||||
hex
|
||||
default 0xce000
|
||||
default 0xfefc0000
|
||||
|
||||
config DCACHE_RAM_SIZE
|
||||
hex
|
||||
|
|
|
|||
|
|
@ -28,5 +28,5 @@ subdirs-y += ../../x86/cache
|
|||
subdirs-y += ../../x86/smm
|
||||
subdirs-y += ../microcode
|
||||
|
||||
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
|
||||
romstage-y += ../car/romstage_legacy.c
|
||||
cpu_incs-y += $(src)/cpu/intel/car/p3/cache_as_ram.S
|
||||
romstage-y += ../car/romstage.c
|
||||
|
|
|
|||
|
|
@ -17,7 +17,11 @@
|
|||
|
||||
#include <arch/io.h>
|
||||
#include <cbmem.h>
|
||||
#include <console/console.h>
|
||||
#include <commonlib/helpers.h>
|
||||
#include <cpu/intel/romstage.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <program_loading.h>
|
||||
#include "i440bx.h"
|
||||
|
||||
void *cbmem_top(void)
|
||||
|
|
@ -62,3 +66,33 @@ void *cbmem_top(void)
|
|||
}
|
||||
return (void *)tom;
|
||||
}
|
||||
|
||||
#define ROMSTAGE_RAM_STACK_SIZE 0x5000
|
||||
|
||||
/* setup_stack_and_mtrrs() determines the stack to use after
|
||||
* cache-as-ram is torn down as well as the MTRR settings to use. */
|
||||
void *setup_stack_and_mtrrs(void)
|
||||
{
|
||||
struct postcar_frame pcf;
|
||||
uintptr_t top_of_ram;
|
||||
|
||||
if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
|
||||
die("Unable to initialize postcar frame.\n");
|
||||
|
||||
/* Cache the ROM as WP just below 4GiB. */
|
||||
postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
|
||||
MTRR_TYPE_WRPROT);
|
||||
|
||||
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
|
||||
postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
|
||||
|
||||
/* Cache CBMEM region as WB. */
|
||||
top_of_ram = (uintptr_t)cbmem_top();
|
||||
postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
|
||||
MTRR_TYPE_WRBACK);
|
||||
|
||||
/* Save the number of MTRRs to setup. Return the stack location
|
||||
* pointing to the number of MTRRs.
|
||||
*/
|
||||
return postcar_commit_mtrrs(&pcf);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue