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mb/google/drallion: Disable GPIO dynamic PM configuration 

BUG=b:144002424
TEST=Ensured no TPM time out issue and system can boot to OS

Change-Id: I7282e6c2d9627846039638bdc0db3ee7ebba5f12
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik 2019-11-28 14:02:10 +05:30 committed by Patrick Georgi
parent 73b1bd7992
commit 54daaecacb
3 changed files with 21 additions and 19 deletions
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12
src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb
View File

@ -212,11 +212,13 @@ chip soc/intel/cannonlake
register "gpio_override_pm" = "1"
# GPIO community PM configuration
register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN"
register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
# Disable dynamic clock gating; with bits 0-5 set in these registers,
# some short interrupt pulses were missed (esp. cr50 irq)
register "gpio_pm[COMM_0]" = "0"
register "gpio_pm[COMM_1]" = "0"
register "gpio_pm[COMM_2]" = "0"
register "gpio_pm[COMM_3]" = "0"
register "gpio_pm[COMM_4]" = "0"
device cpu_cluster 0 on
device lapic 0 on end

16
src/mainboard/google/drallion/variants/drallion/devicetree.cb
View File

@ -209,15 +209,13 @@ chip soc/intel/cannonlake
register "gpio_override_pm" = "1"
# GPIO community PM configuration
register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN |
MISCCFG_GPRTCDLCGEN |
MISCCFG_GSXSLCGEN |
MISCCFG_GPDPCGEN |
MISCCFG_GPDLCGEN"
register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
# Disable dynamic clock gating; with bits 0-5 set in these registers,
# some short interrupt pulses were missed (esp. cr50 irq)
register "gpio_pm[COMM_0]" = "0"
register "gpio_pm[COMM_1]" = "0"
register "gpio_pm[COMM_2]" = "0"
register "gpio_pm[COMM_3]" = "0"
register "gpio_pm[COMM_4]" = "0"
device cpu_cluster 0 on
device lapic 0 on end

12
src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb
View File

@ -215,11 +215,13 @@ chip soc/intel/cannonlake
register "gpio_override_pm" = "1"
# GPIO community PM configuration
register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN"
register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
# Disable dynamic clock gating; with bits 0-5 set in these registers,
# some short interrupt pulses were missed (esp. cr50 irq)
register "gpio_pm[COMM_0]" = "0"
register "gpio_pm[COMM_1]" = "0"
register "gpio_pm[COMM_2]" = "0"
register "gpio_pm[COMM_3]" = "0"
register "gpio_pm[COMM_4]" = "0"
device cpu_cluster 0 on
device lapic 0 on end