soc/intel: fix eist enabling

There was a bug like this for skylake that seems to have been copied to
other SoCs.

Signed-off-by: Matt Delco <delco@chromium.org>
Change-Id: Ib4651eda46a064dfb59797ac8e1cb8c38bb8e38c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/cannonlake/cpu.c

@@ -263,9 +263,10 @@ static void configure_misc(void)
 	msr = rdmsr(IA32_MISC_ENABLE);
 	msr.lo |= (1 << 0);	/* Fast String enable */
 	msr.lo |= (1 << 3);	/* TM1/TM2/EMTTM enable */
+	wrmsr(IA32_MISC_ENABLE, msr);
+
 	/* Set EIST status */
 	cpu_set_eist(conf->eist_enable);
-	wrmsr(IA32_MISC_ENABLE, msr);
 
 	/* Disable Thermal interrupts */
 	msr.lo = 0;

src/soc/intel/icelake/cpu.c

@@ -71,9 +71,10 @@ static void configure_misc(void)
 	msr = rdmsr(IA32_MISC_ENABLE);
 	msr.lo |= (1 << 0);	/* Fast String enable */
 	msr.lo |= (1 << 3);	/* TM1/TM2/EMTTM enable */
+	wrmsr(IA32_MISC_ENABLE, msr);
+
 	/* Set EIST status */
 	cpu_set_eist(conf->eist_enable);
-	wrmsr(IA32_MISC_ENABLE, msr);
 
 	/* Disable Thermal interrupts */
 	msr.lo = 0;

src/soc/intel/skylake/cpu.c

@@ -291,14 +291,11 @@ static void configure_misc(void)
 	msr = rdmsr(IA32_MISC_ENABLE);
 	msr.lo |= (1 << 0);	/* Fast String enable */
 	msr.lo |= (1 << 3);	/* TM1/TM2/EMTTM enable */
-
-	if (conf->eist_enable)
-		msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */
-	else
-		msr.lo &= ~(1 << 16);	/* Enhanced SpeedStep Disable */
-
 	wrmsr(IA32_MISC_ENABLE, msr);
 
+	/* Set EIST status */
+	cpu_set_eist(conf->eist_enable);
+
 	/* Disable Thermal interrupts */
 	msr.lo = 0;
 	msr.hi = 0;

src/soc/intel/tigerlake/cpu.c

@@ -77,9 +77,10 @@ static void configure_misc(void)
 	msr = rdmsr(IA32_MISC_ENABLE);
 	msr.lo |= (1 << 0);	/* Fast String enable */
 	msr.lo |= (1 << 3);	/* TM1/TM2/EMTTM enable */
+	wrmsr(IA32_MISC_ENABLE, msr);
+
 	/* Set EIST status */
 	cpu_set_eist(conf->eist_enable);
-	wrmsr(IA32_MISC_ENABLE, msr);
 
 	/* Disable Thermal interrupts */
 	msr.lo = 0;