soc/intel: fix eist enabling

There was a bug like this for skylake that seems to have been copied to
other SoCs.

Signed-off-by: Matt Delco <delco@chromium.org>
Change-Id: Ib4651eda46a064dfb59797ac8e1cb8c38bb8e38c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Matt Delco 2020-03-09 12:41:09 -07:00 committed by Patrick Georgi
parent 49fb39b783
commit 54e9894353
4 changed files with 9 additions and 9 deletions

View File

@ -263,9 +263,10 @@ static void configure_misc(void)
msr = rdmsr(IA32_MISC_ENABLE); msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 0); /* Fast String enable */
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
wrmsr(IA32_MISC_ENABLE, msr);
/* Set EIST status */ /* Set EIST status */
cpu_set_eist(conf->eist_enable); cpu_set_eist(conf->eist_enable);
wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */ /* Disable Thermal interrupts */
msr.lo = 0; msr.lo = 0;

View File

@ -71,9 +71,10 @@ static void configure_misc(void)
msr = rdmsr(IA32_MISC_ENABLE); msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 0); /* Fast String enable */
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
wrmsr(IA32_MISC_ENABLE, msr);
/* Set EIST status */ /* Set EIST status */
cpu_set_eist(conf->eist_enable); cpu_set_eist(conf->eist_enable);
wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */ /* Disable Thermal interrupts */
msr.lo = 0; msr.lo = 0;

View File

@ -291,14 +291,11 @@ static void configure_misc(void)
msr = rdmsr(IA32_MISC_ENABLE); msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 0); /* Fast String enable */
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
if (conf->eist_enable)
msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
else
msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */
wrmsr(IA32_MISC_ENABLE, msr); wrmsr(IA32_MISC_ENABLE, msr);
/* Set EIST status */
cpu_set_eist(conf->eist_enable);
/* Disable Thermal interrupts */ /* Disable Thermal interrupts */
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;

View File

@ -77,9 +77,10 @@ static void configure_misc(void)
msr = rdmsr(IA32_MISC_ENABLE); msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 0); /* Fast String enable */
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
wrmsr(IA32_MISC_ENABLE, msr);
/* Set EIST status */ /* Set EIST status */
cpu_set_eist(conf->eist_enable); cpu_set_eist(conf->eist_enable);
wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */ /* Disable Thermal interrupts */
msr.lo = 0; msr.lo = 0;