soc/intel/cannonlake: Add FSP UPD for minimum assertion width
Expose the FSP tunables for the chipset minimum assertion width settings which can be configured per-board. The defaults appear to be different from what is listed in the FSP header documentation so I tried to list what the actual default is based on the source rather than what is stated the header comments. Change-Id: Ie0606c2984727adf13c9fb8395586287162e49ca Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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@ -222,6 +222,43 @@ struct soc_intel_cannonlake_config {
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*/
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uint32_t PrmrrSize;
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uint8_t PmTimerDisabled;
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/*
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* SLP_S3 Minimum Assertion Width Policy
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* 1 = 60us
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* 2 = 1ms (default)
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* 3 = 50ms
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* 4 = 2s
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*/
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uint8_t PchPmSlpS3MinAssert;
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/*
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* SLP_S4 Minimum Assertion Width Policy
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* 1 = 1s
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* 2 = 2s
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* 3 = 3s
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* 4 = 4s (default)
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*/
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uint8_t PchPmSlpS4MinAssert;
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/*
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* SLP_SUS Minimum Assertion Width Policy
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* 1 = 0ms
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* 2 = 500ms
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* 3 = 1s (default)
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* 4 = 4s
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*/
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uint8_t PchPmSlpSusMinAssert;
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/*
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* SLP_A Minimum Assertion Width Policy
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* 1 = 0ms
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* 2 = 4s
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* 3 = 98ms (default)
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* 4 = 2s
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*/
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uint8_t PchPmSlpAMinAssert;
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/* Desired platform debug type. */
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enum {
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DebugConsent_Disabled,
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@ -229,6 +229,16 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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/* Power Optimizer */
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params->PchPwrOptEnable = config->dmipwroptimize;
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params->SataPwrOptEnable = config->satapwroptimize;
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/* Apply minimum assertion width settings if non-zero */
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if (config->PchPmSlpS3MinAssert)
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params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert;
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if (config->PchPmSlpS4MinAssert)
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params->PchPmSlpS4MinAssert = config->PchPmSlpS4MinAssert;
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if (config->PchPmSlpSusMinAssert)
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params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert;
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if (config->PchPmSlpAMinAssert)
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params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert;
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}
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/* Mainboard GPIO Configuration */
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