hand crafted mptable
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo
parent
8e79fc3fa8
commit
550999eaca
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@ -1,7 +1,7 @@
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#include <arch/pirq_routing.h>
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#include <device/pci.h>
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#define IRQ_ROUTER_BUS 1
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#define IRQ_ROUTER_BUS 0
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#define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3)
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#define IRQ_ROUTER_VENDOR 0x1022
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#define IRQ_ROUTER_DEVICE 0x746b
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@ -39,8 +39,8 @@ const struct irq_routing_table intel_irq_routing_table = {
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/* AMD-8131 PCI-X Bridge */
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IRQ_SLOT(0x0, 0x00,0x02,0x0, 0,0,0,0),
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/* PCI Slot 1-2 */
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IRQ_SLOT(0x1, 0x02,0x04,0x0, 1,2,3,4),
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IRQ_SLOT(0x2, 0x02,0x03,0x0, 2,3,4,1),
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IRQ_SLOT(0x1, 0x02,0x03,0x0, 1,2,3,4),
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IRQ_SLOT(0x2, 0x02,0x04,0x0, 2,3,4,1),
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/* AMD-8111 PCI Bridge */
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IRQ_SLOT(0x0, 0x00,0x03,0x0, 0,0,0,0),
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/* USB Controller */
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@ -10,11 +10,13 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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static const char oem[8] = "IBM ";
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static const char productid[12] = "E325 ";
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struct mp_config_table *mc;
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unsigned char bus_num;
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unsigned char bus_isa;
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unsigned char bus_8111_0;
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unsigned char bus_8111_1;
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unsigned char bus_8131_1;
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unsigned char bus_8131_2;
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unsigned char bus_8111_1;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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memset(mc, 0, sizeof(*mc));
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@ -39,64 +41,59 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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device_t dev;
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/* 8111 */
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dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
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dev = dev_find_slot(0, PCI_DEVFN(0x03,0));
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if (dev) {
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bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
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bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_isa++;
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}
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else {
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printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
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} else {
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printk_debug("ERROR - could not find PCI 0:03.0, using defaults\n");
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bus_8111_1 = 4;
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bus_isa = 5;
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}
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/* 8131-1 */
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dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
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dev = dev_find_slot(0, PCI_DEVFN(0x01,0));
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if (dev) {
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bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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else {
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printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
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} else {
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printk_debug("ERROR - could not find PCI 0:01.0, using defaults\n");
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bus_8131_1 = 2;
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}
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/* 8131-2 */
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dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
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dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
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if (dev) {
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bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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else {
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printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
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} else {
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printk_debug("ERROR - could not find PCI 0:02.0, using defaults\n");
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bus_8131_2 = 3;
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}
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}
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/* define bus and isa numbers */
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for(bus_num = 0; bus_num < bus_isa; bus_num++) {
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for (bus_num = 0; bus_num < bus_isa; bus_num++) {
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smp_write_bus(mc, bus_num, "PCI ");
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}
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smp_write_bus(mc, bus_isa, "ISA ");
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/* IOAPIC handling */
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/* Legacy IOAPIC #2 */
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smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
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{
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device_t dev;
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uint32_t base;
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/* 8131 apic 3 */
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dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
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/* 8131-1 apic #3 */
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dev = dev_find_slot(0, PCI_DEVFN(0x01,1));
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if (dev) {
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base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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base &= PCI_BASE_ADDRESS_MEM_MASK;
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smp_write_ioapic(mc, 0x03, 0x11, base);
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}
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/* 8131 apic 4 */
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dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
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if (dev) {
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/* 8131-2 apic #4 */
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dev = dev_find_slot(0, PCI_DEVFN(0x02,1));
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if (dev) {
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base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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base &= PCI_BASE_ADDRESS_MEM_MASK;
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smp_write_ioapic(mc, 0x04, 0x11, base);
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@ -104,122 +101,66 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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}
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/* ISA backward compatibility interrupts */
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smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, 0x02, 0x00);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x01, 0x02, 0x01);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, 0x02, 0x02);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x03, 0x02, 0x03);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x04, 0x02, 0x04);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x05, 0x02, 0x05);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x06, 0x02, 0x06);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x07, 0x02, 0x07);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x08, 0x02, 0x08);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x09, 0x02, 0x09);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0a, 0x02, 0x0a);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0b, 0x02, 0x0b);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0c, 0x02, 0x0c);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0d, 0x02, 0x0d);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0e, 0x02, 0x0e);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0f, 0x02, 0x0f);
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smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, 0x02, 0x00);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x01, 0x02, 0x01);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, 0x02, 0x02);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x03, 0x02, 0x03);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x04, 0x02, 0x04);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x05, 0x02, 0x05);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x06, 0x02, 0x06);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x07, 0x02, 0x07);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x08, 0x02, 0x08);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x09, 0x02, 0x09);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0a, 0x02, 0x0a);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0b, 0x02, 0x0b);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0c, 0x02, 0x0c);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0d, 0x02, 0x0d);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0e, 0x02, 0x0e);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0f, 0x02, 0x0f);
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/* Standard local interrupt assignments */
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smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, MP_APIC_ALL, 0x00);
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smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, MP_APIC_ALL, 0x01);
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/* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
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/* Integrated SMBus 2.0 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|3, 0x2, 0x13);
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/* Integrated AMD AC97 Audio */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|1, 0x2, 0x11);
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/* Integrated AMD USB */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x00<<2)|3, 0x2, 0x13);
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/* PCI Slot 1 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (1<<2)|0, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (1<<2)|1, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (1<<2)|2, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (1<<2)|3, 0x02, 0x10);
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/* On board ATI Rage XL */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x2, 0x10);
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/* PCI Slot 2 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (2<<2)|0, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (2<<2)|1, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (2<<2)|2, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (2<<2)|3, 0x02, 0x11);
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/* On board Broadcom nics */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x3, 0x00);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x3, 0x01);
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/* PCI Slot 3 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (1<<2)|0, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (1<<2)|1, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (1<<2)|2, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (1<<2)|3, 0x02, 0x10);
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/* On board LSI SCSI */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x3, 0x02);
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/* PCI Slot 4 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (2<<2)|0, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (2<<2)|1, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (2<<2)|2, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (2<<2)|3, 0x02, 0x11);
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/* PCI Slot 1 PCIX */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|0, 0x2, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|1, 0x2, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|2, 0x2, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|3, 0x2, 0x13);
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/* PCI Slot 5 */
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#warning "FIXME get the irqs right, it's just hacked to work for now"
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (5<<2)|0, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (5<<2)|1, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (5<<2)|2, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (5<<2)|3, 0x02, 0x10);
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/* PCI Slot 2 PCIX */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|0, 0x2, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|1, 0x2, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|2, 0x2, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|3, 0x2, 0x10);
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/* PCI Slot 6 */
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#warning "FIXME get the irqs right, it's just hacked to work for now"
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (4<<2)|0, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (4<<2)|1, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (4<<2)|2, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (4<<2)|3, 0x02, 0x13);
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/* On board nics */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (3<<2)|0, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (4<<2)|0, 0x02, 0x13);
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/* Standard local interrupt assignments:
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* Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x00);
|
||||
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x01);
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue