mb/google/corsola: Fully calibrate DRAM

Initialize and calibrate DRAM in romstage.

DRAM full calibration logs:
dram_init: dram init end (result: 1)
DRAM-K: Full calibration passed in 20014 msecs

TEST=DRAM full calibration pass.
BUG=b:202871018

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I80a18a8be5b1d47a5f0f7afed9601c0884e69035
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

src/mainboard/google/corsola/Makefile.inc

@@ -11,6 +11,7 @@ romstage-y += boardid.c
 romstage-y += chromeos.c
 romstage-y += regulator.c
 romstage-y += romstage.c
+romstage-y += sdram_configs.c
 
 ramstage-y += memlayout.ld
 ramstage-y += boardid.c

src/mainboard/google/corsola/romstage.c

@@ -3,6 +3,7 @@
 #include <arch/stages.h>
 #include <console/console.h>
 #include <delay.h>
+#include <soc/emi.h>
 #include <soc/mt6366.h>
 #include <soc/pll_common.h>
 #include <soc/regulator.h>
@@ -26,4 +27,5 @@ void platform_romstage_main(void)
 	mt6366_init();
 	raise_little_cpu_freq();
 	rtc_boot();
+	mtk_dram_init();
 }

src/mainboard/google/corsola/sdram_configs.c

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/dramc_param.h>
+
+const struct sdram_info *get_sdram_config(void)
+{
+	/*
+	 * The MT8186 platform supports "dram adaptive" feature to
+	 * automatically detect dram information, including channel, rank, die size...,
+	 * and can automatically configure EMI settings.
+	 * So we will be passing a placeholder param blob.
+	 */
+	static struct sdram_info params;
+	return &params;
+}