soc/intel/common: Add edge trigger configuartion for IOAPIC IRQ mode
Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85daa Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/26730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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@ -284,6 +284,9 @@
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#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \
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PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE)
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#define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \
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PAD_CFG_GPI_APIC(pad, pull, rst, EDGE_SINGLE, INVERT)
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/* General purpose input, routed to SMI */
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#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \
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_PAD_CFG_STRUCT(pad, \
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