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soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage 

This patch sets up cse_fw_sync() call in the romstage.The cse_fw_sync()
must be called after DRAM initialization.

BUG=b:174694480
Test=Verified on Drawlet

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48280
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sridhar Siricilla 2020-12-04 02:24:31 +05:30 committed by Furquan Shaikh
parent 1a2b702848
commit 551bd92b2b
1 changed files with 11 additions and 1 deletions
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12
src/soc/intel/jasperlake/romstage/romstage.c
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@ -135,6 +135,16 @@ void mainboard_romstage_entry(void)
s3wake = pmc_fill_power_state(ps) == ACPI_S3; s3wake = pmc_fill_power_state(ps) == ACPI_S3;
fsp_memory_init(s3wake); fsp_memory_init(s3wake);
pmc_set_disb(); pmc_set_disb();
if (!s3wake) if (!s3wake) {
/*
* cse_fw_sync() must be called after DRAM initialization as
* HMRFPO_ENABLE HECI command (which is used by cse_fw_sync())
* is expected to be executed after DRAM initialization.
*/
if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
cse_fw_sync();
save_dimm_info(); save_dimm_info();
}
} }