broadwell: Changes from 2.2.0 ref code

- The SATA CAP register setup was moved outside the refcode blob we run
so it needs to be set up by coreboot again...
- Slight tweak to fast ramp voltage for broadwell CPU

BUG=chrome-os-partner:25491
BRANCH=None
TEST=Build and boot on samus

Original-Change-Id: I7bdc0811ad8f28ab0912972036dca59d229b0173
Original-CSigned-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-CReviewed-on: https://chromium-review.googlesource.com/214024
Original-CReviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 5d166a0c4d206eaa885ecebaa0c3cefefdc59280)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Id58d3bee5e713139edf6e8fda8cdf4c48ba95bd1
Reviewed-on: http://review.coreboot.org/8964
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

src/soc/intel/broadwell/cpu.c

@@ -246,8 +246,11 @@ static void initialize_vr_config(void)
 	msr = rdmsr(MSR_VR_MISC_CONFIG2);
 	msr.lo &= ~0xffff;
 	/* Allow CPU to control minimum voltage completely (15:8) and
-	 * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */
-	msr.lo |= 0x006f;
+	 * set the fast ramp voltage in 10mV steps. */
+	if (cpu_family_model() == BROADWELL_FAMILY_ULT)
+		msr.lo |= 0x006a; /* 1.56V */
+	else
+		msr.lo |= 0x006f; /* 1.60V */
 	wrmsr(MSR_VR_MISC_CONFIG2, msr);
 }
 

src/soc/intel/broadwell/sata.c

@@ -92,6 +92,13 @@ static void sata_init(struct device *dev)
 	abar = (u8 *)(pci_read_config32(dev, PCI_BASE_ADDRESS_5));
 	printk(BIOS_DEBUG, "ABAR: %p\n", abar);
 
+	/* CAP (HBA Capabilities) : enable power management */
+	reg32 = read32(abar + 0x00);
+	reg32 |= 0x0c006000;  /* set PSC+SSC+SALP+SSS */
+	reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
+	reg32 |= (1 << 18);   /* SAM: SATA AHCI MODE ONLY */
+	write32(abar + 0x00, reg32);
+
 	/* PI (Ports implemented) */
 	write32(abar + 0x0c, config->sata_port_map);
 	(void) read32(abar + 0x0c); /* Read back 1 */