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Port persimmon r6584 and r6601 to e350m1: SPI prefetch early 

Enable SPI cacheline prefetch early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marshall Buschman 2011-06-04 15:45:12 +00:00 committed by Peter Stuge
parent fd460e620e
commit 552ad9f75e
1 changed files with 7 additions and 0 deletions
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7
src/mainboard/asrock/e350m1/romstage.c
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@ -50,6 +50,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
__writemsr (0xc0010062, 0);
// early enable of PrefetchEnSPIFromHost
if (boot_cpu())
{
__outdword (0xcf8, 0x8000a3b8);
__outdword (0xcfc, __indword (0xcfc) | 1 << 24);
}
// early enable of SPI 33 MHz fast mode read
if (boot_cpu())
{