soc/intel/skylake/chip.h: Use boolean type where applicable
Change-Id: Ic40917689092e8d897a3ba92ac767cdb3b595eb3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75880 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Felix Singer
Felix Singer
parent
56167c5757
commit
552da5685e
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@ -60,13 +60,13 @@ struct soc_intel_skylake_config {
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bool s0ix_enable;
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/* Enable DPTF support */
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int dptf_enable;
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bool dptf_enable;
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/* Deep SX enables */
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int deep_s3_enable_ac;
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int deep_s3_enable_dc;
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int deep_s5_enable_ac;
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int deep_s5_enable_dc;
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bool deep_s3_enable_ac;
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bool deep_s3_enable_dc;
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bool deep_s5_enable_ac;
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bool deep_s5_enable_dc;
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/*
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* Deep Sx Configuration
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@ -95,15 +95,15 @@ struct soc_intel_skylake_config {
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} SaGv;
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/* Enable/disable Rank Margin Tool */
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u8 RMT;
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bool RMT;
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/* Disable Command TriState */
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u8 CmdTriStateDis;
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bool CmdTriStateDis;
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/* Lan */
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u8 EnableLanLtr;
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u8 EnableLanK1Off;
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u8 LanClkReqSupported;
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bool EnableLanLtr;
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bool EnableLanK1Off;
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bool LanClkReqSupported;
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u8 LanClkReqNumber;
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/* SATA related */
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@ -111,15 +111,15 @@ struct soc_intel_skylake_config {
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SATA_AHCI = 0,
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SATA_RAID = 1,
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} SataMode;
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u8 SataSalpSupport;
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u8 SataPortsEnable[8];
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u8 SataPortsDevSlp[8];
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u8 SataPortsSpinUp[8];
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u8 SataPortsHotPlug[8];
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bool SataSalpSupport;
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bool SataPortsEnable[8];
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bool SataPortsDevSlp[8];
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bool SataPortsSpinUp[8];
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bool SataPortsHotPlug[8];
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u8 SataSpeedLimit;
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/* Audio related */
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u8 DspEnable;
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bool DspEnable;
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/* HDA Virtual Channel Type Select */
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enum {
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@ -140,7 +140,7 @@ struct soc_intel_skylake_config {
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u32 TraceHubMemReg1Size;
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/* DCI Enable/Disable */
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u8 PchDciEn;
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bool PchDciEn;
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/*
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* PCIe Root Port configuration:
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@ -175,14 +175,14 @@ struct soc_intel_skylake_config {
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* 0: Disable Root Port
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* 1: Enable Root Port
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*/
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u8 PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
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bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
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/*
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* Enable/Disable Clk-req support for Root Port
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* 0: Disable Clk-Req
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* 1: Enable Clk-req
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*/
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u8 PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS];
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bool PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS];
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/*
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* Clk-req source for Root Port
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@ -199,17 +199,17 @@ struct soc_intel_skylake_config {
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* 0: Disable AER
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* 1: Enable AER
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*/
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u8 PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
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bool PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
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/*
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* Enable/Disable Latency Tolerance Reporting for Root Port
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* 0: Disable LTR
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* 1: Enable LTR
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*/
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u8 PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
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bool PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
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/* Enable/Disable HotPlug support for Root Port */
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u8 PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
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bool PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
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/* PCIE RP Max Payload, Max Payload Size supported */
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enum {
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@ -238,7 +238,7 @@ struct soc_intel_skylake_config {
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/* USB related */
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struct usb2_port_config usb2_ports[16];
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struct usb3_port_config usb3_ports[10];
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u8 SsicPortEnable;
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bool SsicPortEnable;
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/*
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* SerialIO device mode selection:
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@ -271,8 +271,8 @@ struct soc_intel_skylake_config {
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enum skylake_i2c_voltage i2c_voltage[CONFIG_SOC_INTEL_I2C_DEV_MAX];
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/* eMMC and SD */
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u8 ScsEmmcHs400Enabled;
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u8 EmmcHs400DllNeed;
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bool ScsEmmcHs400Enabled;
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bool EmmcHs400DllNeed;
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u8 ScsEmmcHs400RxStrobeDll1;
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u8 ScsEmmcHs400TxDataDll;
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@ -283,7 +283,7 @@ struct soc_intel_skylake_config {
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Display_Auto,
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Display_Switchable,
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} PrimaryDisplay;
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u8 SkipExtGfxScan;
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bool SkipExtGfxScan;
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/* GPIO IRQ Route The valid values is 14 or 15*/
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u8 GpioIrqSelect;
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@ -291,34 +291,34 @@ struct soc_intel_skylake_config {
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u8 SciIrqSelect;
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/* TCO IRQ Select The valid values is 9, 10, 11, 20 21, 22, 23*/
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u8 TcoIrqSelect;
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u8 TcoIrqEnable;
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bool TcoIrqEnable;
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/* Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.*/
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u8 LockDownConfigGlobalSmi;
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bool LockDownConfigGlobalSmi;
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/*
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* Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh
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* in the upper and lower 128-byte bank of RTC RAM.
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*/
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u8 LockDownConfigRtcLock;
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bool LockDownConfigRtcLock;
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/*
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* Determine if WLAN wake from Sx, corresponds to the
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* HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
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*/
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u8 PchPmWoWlanEnable;
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bool PchPmWoWlanEnable;
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/*
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* Determine if WLAN wake from DeepSx, corresponds to
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* the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register.
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*/
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u8 PchPmWoWlanDeepSxEnable;
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bool PchPmWoWlanDeepSxEnable;
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/*
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* Corresponds to the "WOL Enable Override" bit in the General PM
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* Configuration B (GEN_PMCON_B) register
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*/
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u8 WakeConfigWolEnableOverride;
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bool WakeConfigWolEnableOverride;
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/* Determine if enable PCIe to wake from deep Sx*/
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u8 WakeConfigPcieWakeFromDeepSx;
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bool WakeConfigPcieWakeFromDeepSx;
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/* Deep Sx Policy. Values 0: PchDeepSxPolDisable,
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* 1: PchDpS5BatteryEn, 2: PchDpS5AlwaysEn, 3: PchDpS4S5BatteryEn,
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* 4: PchDpS4S5AlwaysEn, 5: PchDpS3S4S5BatteryEn, 6: PchDpS3S4S5AlwaysEn
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@ -360,7 +360,7 @@ struct soc_intel_skylake_config {
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* SLP_X Stretching After SUS Well Power Up. Values 0: Disabled,
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* 1: Enabled
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*/
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u8 PmConfigSlpStrchSusUp;
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bool PmConfigSlpStrchSusUp;
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/*
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* PCH power button override period.
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* Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s
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@ -372,7 +372,7 @@ struct soc_intel_skylake_config {
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* Indicates platform supports VCCPrim_Core Voltage Margining
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* in SLP_S0# asserted state.
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*/
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u8 PchPmSlpS0VmEnable;
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bool PchPmSlpS0VmEnable;
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enum {
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RESET_POWER_CYCLE_DEFAULT = 0,
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@ -407,7 +407,7 @@ struct soc_intel_skylake_config {
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u8 SendVrMbxCmd;
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/* Enable/Disable host reads to PMC XRAM registers */
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u8 PchPmPmcReadDisable;
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bool PchPmPmcReadDisable;
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/*
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* Use SD card detect GPIO with default config:
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@ -434,7 +434,7 @@ struct soc_intel_skylake_config {
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* 0b - Disable
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* 1b - Enable noise mitigation
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*/
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u8 AcousticNoiseMitigation;
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bool AcousticNoiseMitigation;
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/*
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* Disable Fast Package C-state ramping
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@ -442,9 +442,9 @@ struct soc_intel_skylake_config {
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* 0b - Enabled
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* 1b - Disabled
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*/
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u8 FastPkgCRampDisableIa;
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u8 FastPkgCRampDisableGt;
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u8 FastPkgCRampDisableSa;
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bool FastPkgCRampDisableIa;
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bool FastPkgCRampDisableGt;
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bool FastPkgCRampDisableSa;
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/*
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* Adjust the VR slew rates
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@ -462,7 +462,7 @@ struct soc_intel_skylake_config {
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* 1b - Enabled
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* 0b - Disabled
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*/
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u8 eist_enable;
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bool eist_enable;
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/*
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* Activates VR mailbox command for Intersil VR C-state issues.
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