soc/samsung/exynos5250: Drop dead code
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I4772680875b20308e57da073bbcdc4597aeed893 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43215 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -19,20 +19,6 @@ static void reset_phy_ctrl(void)
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write32(&exynos_clock->lpddr3phy_ctrl,
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LPDDR3PHY_CTRL_PHY_RESET_DISABLE);
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#if 0
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/*
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* For proper memory initialization there should be a minimum delay of
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* 500us after the LPDDR3PHY_CTRL_PHY_RESET signal.
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* The below value is an approximate value whose calculation in done
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* considering that sdelay takes 2 instruction for every 1 delay cycle.
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* And assuming each instruction takes 1 clock cycle i.e 1/(1.7 Ghz)sec
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* So for 500 usec, the number of delay cycle should be
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* (500 * 10^-6) * (1.7 * 10^9) / 2 = 425000
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*
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* TODO(hatim.rv@samsung.com): Implement the delay using timer/counter
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*/
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sdelay(425000);
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#endif
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udelay(500);
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}
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@ -140,14 +140,6 @@ void fb_init(unsigned long int fb_size, void *lcdbase,
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write32(&exynos_fimd->dpclkcon, 1 << 1);
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}
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#ifdef UNUSED_CODE
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void exynos_fimd_disable(void)
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{
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write32(&exynos_fimd->wincon0, 0);
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clrbits32(&exynos_fimd->shadowcon, CHANNEL0_EN);
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}
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#endif
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/*
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* Configure DP in slave mode and wait for video stream.
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*
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@ -13,34 +13,6 @@
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#define RX_FIFO_FULL_MASK (1 << 8)
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#define TX_FIFO_FULL_MASK (1 << 24)
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#if 0
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/*
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* The coefficient, used to calculate the baudrate on S5P UARTs is
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* calculated as
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* C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
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* however, section 31.6.11 of the datasheet doesn't recommend using 1 for 1,
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* 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
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*/
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static const int udivslot[] = {
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0,
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0x0080,
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0x0808,
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0x0888,
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0x2222,
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0x4924,
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0x4a52,
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0x54aa,
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0x5555,
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0xd555,
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0xd5d5,
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0xddd5,
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0xdddd,
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0xdfdd,
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0xdfdf,
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0xffdf,
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};
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#endif
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static void serial_setbrg_dev(struct s5p_uart *uart)
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{
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u32 uclk;
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@ -51,18 +23,6 @@ static void serial_setbrg_dev(struct s5p_uart *uart)
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val = uclk / get_uart_baudrate();
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write32(&uart->ubrdiv, val / 16 - 1);
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/*
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* FIXME(dhendrix): the original uart.h had a "br_rest" value which
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* does not seem relevant to the exynos5250... not entirely sure
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* where/if we need to worry about it here
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*/
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#if 0
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if (s5p_uart_divslot())
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writel(udivslot[val % 16], &uart->rest.slot);
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else
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writeb(val % 16, &uart->rest.value);
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#endif
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}
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/*
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