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nehalem: Make UMA size configurable in CMOS. 

All modes tested on X201.

Change-Id: I23df81523196ea3f5fdb10eb04f4496c00aaeb9f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6481
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Vladimir Serbinenko 2014-08-03 14:51:00 +02:00
parent 63e1948643
commit 55391c422f
3 changed files with 34 additions and 10 deletions
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15
src/mainboard/lenovo/x201/cmos.layout
View File

@ -97,7 +97,13 @@ entries
419 1 e 1 power_management_beeps
420 1 e 1 low_battery_beep
421 1 e 9 sata_mode
#422 562 r 0 unused
#422 2 r 0 unused
# coreboot config options: northbridge
424 3 e 10 gfx_uma_size
#427 557 r 0 unused
# coreboot config options: check sums
984 16 h 0 check_sum
@ -138,6 +144,13 @@ enumerations
8 1 Primary
9 0 AHCI
9 1 Compatible
10 0 32M
10 1 48M
10 2 64M
10 3 128M
10 5 96M
10 6 160M
# -----------------------------------------------------------------
checksums

9
src/mainboard/packardbell/ms2290/cmos.layout
View File

@ -84,6 +84,9 @@ entries
409 2 e 7 power_on_after_fail
411 1 e 9 sata_mode
# coreboot config options: northbridge
424 3 e 10 gfx_uma_size
# coreboot config options: check sums
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
@ -123,6 +126,12 @@ enumerations
8 1 Primary
9 0 AHCI
9 1 Compatible
10 0 32M
10 1 48M
10 2 64M
10 3 128M
10 5 96M
10 6 160M
# -----------------------------------------------------------------
checksums

20
src/northbridge/intel/nehalem/raminit.c
View File

@ -3796,6 +3796,8 @@ static void dmi_setup(void)
void chipset_init(const int s3resume)
{
u8 x2ca8;
u16 ggc;
u8 gfxsize;
x2ca8 = read_mchbar8(0x2ca8);
if ((x2ca8 & 1) || (x2ca8 == 8 && !s3resume)) {
@ -3825,13 +3827,15 @@ void chipset_init(const int s3resume)
write_mchbar16(0x1170, 0xb880);
read_mchbar8(0x1210);
write_mchbar8(0x1210, 0x84);
pcie_read_config8(NORTHBRIDGE, D0F0_GGC); // = 0x52
pcie_write_config8(NORTHBRIDGE, D0F0_GGC, 0x2);
pcie_read_config8(NORTHBRIDGE, D0F0_GGC); // = 0x2
pcie_write_config8(NORTHBRIDGE, D0F0_GGC, 0x52);
pcie_read_config16(NORTHBRIDGE, D0F0_GGC); // = 0xb52
pcie_write_config16(NORTHBRIDGE, D0F0_GGC, 0xb52);
if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
/* 0 for 32MB */
gfxsize = 0;
}
ggc = 0xb00 | ((gfxsize + 5) << 4);
pcie_write_config16(NORTHBRIDGE, D0F0_GGC, ggc | 2);
u16 deven;
deven = pcie_read_config16(NORTHBRIDGE, D0F0_DEVEN); // = 0x3
@ -3854,9 +3858,7 @@ void chipset_init(const int s3resume)
read_mchbar32(0x30);
write_mchbar32(0x30, 0x40);
pcie_read_config8(SOUTHBRIDGE, 0x8); // = 0x6
pcie_read_config16(NORTHBRIDGE, D0F0_GGC); // = 0xb52
pcie_write_config16(NORTHBRIDGE, D0F0_GGC, 0xb50);
pcie_write_config16(NORTHBRIDGE, D0F0_GGC, ggc);
gav(read32(DEFAULT_RCBA | 0x3428));
write32(DEFAULT_RCBA | 0x3428, 0x1d);
}