diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig
index ce320813c0..58af8df4dd 100644
--- a/src/mainboard/google/poppy/Kconfig
+++ b/src/mainboard/google/poppy/Kconfig
@@ -22,7 +22,16 @@ config DEVICETREE
 	string
 	default "variants/baseboard/devicetree.cb"
 
+config DRIVER_TPM_I2C_BUS
+	depends on POPPY_USE_I2C_TPM
+	default 0x4
+
+config DRIVER_TPM_I2C_ADDR
+	depends on POPPY_USE_I2C_TPM
+	default 0x50
+
 config DRIVER_TPM_SPI_BUS
+	depends on POPPY_USE_SPI_TPM
 	default 0x1
 
 config GBB_HWID
@@ -56,6 +65,14 @@ config MAX_CPUS
 	int
 	default 8
 
+# Select this option to enable use of cr50 I2C TPM on poppy.
+config POPPY_USE_I2C_TPM
+	bool
+	default n
+	select I2C_TPM
+	select MAINBOARD_HAS_I2C_TPM_CR50
+	select TPM2
+
 # Select this option to enable use of cr50 SPI TPM on poppy.
 # This option is disabled by default.
 config POPPY_USE_SPI_TPM
@@ -65,6 +82,10 @@ config POPPY_USE_SPI_TPM
 	select SPI_TPM
 	select TPM2
 
+config TPM_TIS_ACPI_INTERRUPT
+	int
+	default 64  # GPE0_DW2_00 (GPP_E0)
+
 config VARIANT_DIR
 	string
 	default "poppy" if BOARD_GOOGLE_POPPY
@@ -76,11 +97,4 @@ config VBOOT
 	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 	select VBOOT_LID_SWITCH
 
-config DRIVER_TPM_SPI_BUS
-	default 0x1
-
-config TPM_TIS_ACPI_INTERRUPT
-	int
-	default 64  # GPE0_DW2_00 (GPP_E0)
-
 endif # BOARD_GOOGLE_BASEBOARD_POPPY
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index d232028544..4e3ffaf68c 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -154,7 +154,7 @@ chip soc/intel/skylake
 	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Empty
 
 	register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"		# Touchscreen
-	register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"		# NFC
+	register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"		# H1
 	register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"		# Camera
 	register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"		# Pen
 	register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"		# Camera
@@ -167,6 +167,12 @@ chip soc/intel/skylake
 		 .early_init = 1,
 	}"
 
+	# Configure I2C1 for cr50 TPM. Early init is required to set up a BAR
+	# for TPM communication before memory is up.
+	register "i2c[1]" = "{
+		 .early_init = 1,
+	}"
+
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
 	register "SerialIoDevMode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c
index fcbbb1d554..2be9d0f86f 100644
--- a/src/mainboard/google/poppy/variants/baseboard/gpio.c
+++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c
@@ -92,6 +92,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 	/* B14 : SPKR ==> NC */
 	PAD_CFG_NC(GPP_B14),
+#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)
 	/* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */
 	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
 	/* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */
@@ -100,6 +101,16 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 	/* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+#else
+	/* B15 : GSPI0_CS# ==> NC */
+	PAD_CFG_NC(GPP_B15),
+	/* B16 : GSPI0_CLK ==> NC */
+	PAD_CFG_NC(GPP_B16),
+	/* B17 : GSPI0_MISO ==> NC */
+	PAD_CFG_NC(GPP_B17),
+	/* B18 : GSPI0_MOSI ==> NC */
+	PAD_CFG_NC(GPP_B18),
+#endif
 	/* B19 : GSPI1_CS# ==> PCH_SPI_FP_CS_L */
 	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
 	/* B20 : GSPI1_CLK ==> PCH_SPI_FP_CLK */
@@ -147,10 +158,17 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 	/* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */
 	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM)
 	/* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
 	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 	/* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
 	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+#else
+	/* C18 : I2C1_SDA ==> NC */
+	PAD_CFG_NC(GPP_C18),
+	/* C19 : I2C1_SCL ==> NC */
+	PAD_CFG_NC(GPP_C19),
+#endif
 	/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
 	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 	/* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
@@ -353,6 +371,7 @@ static const struct pad_config gpio_table[] = {
 
 /* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
+#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)
 	/* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */
 	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
 	/* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */
@@ -361,11 +380,14 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 	/* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+#endif
 
+#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM)
 	/* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
 	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 	/* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
 	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+#endif
 
 	/* Ensure UART pins are in native mode for H1. */
 	/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */