Ryu: Rewrite I2C6 mux init

Do the absolute minimum needed to allow the DPAUX mux ctl write
for I2C6. This leaves HOST1X off (reset and clock disabled) to
avoid a conflict with any kernel display driver init.

I2C6 init/enable will be moved to ramstage in the next CL.

BUG=chrome-os-partner:31820
BRANCH=none
TEST=Dumped Speaker Driver (AD SSM4567) regs on Ryu, looks good.

Change-Id: I42106778a26c5a1d1483cc308b8314599c391539
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 24a9ebfda31c620b24e5c765dc950b87e3e5587b
Original-Change-Id: I0760222f1d7ccee207ae9871aeed3e2ddbca3dca
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/218900
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9093
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/mainboard/google/rush_ryu/romstage.c

@@ -24,7 +24,6 @@
 #include <soc/padconfig.h>
 #include <soc/nvidia/tegra/i2c.h>
 #include <soc/romstage.h>
-
 #include "gpio.h"
 #include "pmic.h"
 
@@ -93,6 +92,7 @@ void romstage_mainboard_init(void)
 	/* Bring up controller interfaces for ramstage loading. */
 	soc_configure_funits(funits, ARRAY_SIZE(funits));
 	soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
+	soc_configure_i2c6pad();
 
 	/* TPM */
 	i2c_init(I2C3_BUS);

src/soc/nvidia/tegra132/clk_rst.h

@@ -133,7 +133,7 @@ struct  __attribute__ ((__packed__)) clk_rst_ctlr {
 	u32 clk_out_enb_x;		/* _CLK_OUT_ENB_X_0,        0x280 */
 	u32 clk_enb_x_set;		/* _CLK_ENB_X_SET_0,        0x284 */
 	u32 clk_enb_x_clr;		/* _CLK_ENB_X_CLR_0,        0x288 */
-	u32 rst_devices_x;		/* _RST_DEVICES_X_0,        0x28c */
+	u32 rst_dev_x;			/* _RST_DEVICES_X_0,        0x28c */
 	u32 rst_dev_x_set;		/* _RST_DEV_X_SET_0,        0x290 */
 	u32 rst_dev_x_clr;		/* _RST_DEV_X_CLR_0,        0x294 */
 	u32 _rsv19[23];			/*                      0x298-2f0 */

src/soc/nvidia/tegra132/i2c6.c

@@ -51,15 +51,19 @@ static void remove_clamps(int id)
 		;
 }
 
-static void enable_sor_periphs(void)
+static void enable_sor_periph_clocks(void)
 {
-	u32 lclks = CLK_L_HOST1X;
+	setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_HOST1X);
-	u32 hclks = CLK_H_MIPI_CAL | CLK_H_HDMI | CLK_H_DSI;
+	setbits_le32(&clk_rst->clk_out_enb_x, CLK_X_DPAUX);
-	u32 uclks = CLK_U_DSIB;
-	u32 wclks = CLK_W_DP2 | CLK_W_HDA2HDMICODEC;
-	u32 xclks = CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_HDMI_AUDIO;
 
-	clock_enable(lclks, hclks, uclks, 0, wclks, xclks);
+	/* Give clocks time to stabilize. */
+	udelay(IO_STABILIZATION_DELAY);
+}
+
+static void disable_sor_periph_clocks(void)
+{
+	clrbits_le32(&clk_rst->clk_out_enb_l, CLK_L_HOST1X);
+	clrbits_le32(&clk_rst->clk_out_enb_x, CLK_X_DPAUX);
 
 	/* Give clocks time to stabilize. */
 	udelay(IO_STABILIZATION_DELAY);
@@ -67,32 +71,42 @@ static void enable_sor_periphs(void)
 
 static void unreset_sor_periphs(void)
 {
-	u32 lclks = CLK_L_HOST1X;
+	clrbits_le32(&clk_rst->rst_dev_l, CLK_L_HOST1X);
-	u32 hclks = CLK_H_MIPI_CAL | CLK_H_HDMI | CLK_H_DSI;
+	clrbits_le32(&clk_rst->rst_dev_x, CLK_X_DPAUX);
-	u32 uclks = CLK_U_DSIB;
-	u32 wclks = CLK_W_DP2 | CLK_W_HDA2HDMICODEC;
-	u32 xclks = CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_HDMI_AUDIO;
-
-	clock_clear_reset(lclks, hclks, uclks, 0, wclks, xclks);
 }
 
 void soc_configure_i2c6pad(void)
 {
 	/*
 	 * I2C6 on Tegra124/132 requires some special init.
-	 * The SOR block must be unpowergated, and several
+	 * The SOR block must be unpowergated, and a couple of
 	 * display-based peripherals must be clocked and taken
 	 * out of reset so that a DPAUX register can be
 	 * configured to enable the I2C6 mux routing.
+	 * Afterwards, we can disable clocks to the display blocks
+	 * and put Host1X back in reset. DPAUX must remain out of
+	 * reset and the SOR partition must remained unpowergated.
 	 */
 	power_ungate_partition(POWER_PARTID_SOR);
-	enable_sor_periphs();
-	remove_clamps(POWER_PARTID_SOR);
-	unreset_sor_periphs();
 
 	/* Host1X needs a valid clock source so DPAUX can be accessed */
 	clock_configure_source(host1x, PLLP, 204000);
 
+	enable_sor_periph_clocks();
+	remove_clamps(POWER_PARTID_SOR);
+	unreset_sor_periphs();
+
 	/* Now we can write the I2C6 mux in DPAUX */
 	write32(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL);
+
+	/*
+	 * Delay before turning off Host1X/DPAUX clocks.
+	 * This delay is needed to keep the sequence from
+	 * hanging the system.
+	 */
+	udelay(CLOCK_PLL_STABLE_DELAY_US);
+
+	/* Stop Host1X/DPAUX clocks and reset Host1X */
+	disable_sor_periph_clocks();
+	setbits_le32(&clk_rst->rst_dev_l, CLK_L_HOST1X);
 }