Add support for the SMSC LPC47n227 SuperI/O chip
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
7a3d095213
commit
55426dfd57
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@ -10,5 +10,7 @@ config SUPERIO_SMSC_LPC47M15X
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bool
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config SUPERIO_SMSC_LPC47N217
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bool
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config SUPERIO_SMSC_LPC47N227
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bool
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config SUPERIO_SMSC_SMSCSUPERIO
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bool
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@ -4,4 +4,5 @@ subdirs-y += lpc47b397
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subdirs-y += lpc47m10x
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subdirs-y += lpc47m15x
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subdirs-y += lpc47n217
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subdirs-y += lpc47n227
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subdirs-y += smscsuperio
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@ -0,0 +1,21 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config chip.h
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object superio.o
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@ -0,0 +1,20 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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obj-$(CONFIG_SUPERIO_SMSC_LPC47N227) += superio.o
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@ -0,0 +1,29 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/device.h>
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#include <pc80/keyboard.h>
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#include <uart8250.h>
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extern struct chip_operations superio_smsc_lpc47n227_ops;
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struct superio_smsc_lpc47n227_config {
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struct uart8250 com1, com2;
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struct pc_keyboard keyboard;
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};
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@ -0,0 +1,29 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Since the LPC47N227 does not have logical devices but a flat configuration
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* space, these are arbitrary, but must match declarations in the mainboard
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* devicetree.cb
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*/
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#define LPC47N227_PP 1 /* Parallel Port */
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#define LPC47N227_SP1 2 /* COM1 */
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#define LPC47N227_SP2 3 /* COM2 */
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#define LPC47N227_KBDC 5 /* Keyboard */
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#define LPC47N227_MAX_CONFIG_REGISTER 0x39
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@ -0,0 +1,150 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2005 Digital Design Corporation
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Pre-RAM driver for SMSC LPC47N227 Super I/O chip. */
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#include <arch/romcc_io.h>
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#include "lpc47n227.h"
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//----------------------------------------------------------------------------------
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// Function: pnp_enter_conf_state
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// Parameters: dev - high 8 bits = Super I/O port
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// Return Value: None
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// Description: Enable access to the LPC47N227's configuration registers.
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//
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static inline void pnp_enter_conf_state(device_t dev)
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{
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unsigned port = dev >> 8;
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outb(0x55, port);
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}
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//----------------------------------------------------------------------------------
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// Function: pnp_exit_conf_state
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// Parameters: dev - high 8 bits = Super I/O port
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// Return Value: None
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// Description: Disable access to the LPC47N227's configuration registers.
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//
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static void pnp_exit_conf_state(device_t dev)
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{
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unsigned port = dev >> 8;
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outb(0xaa, port);
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}
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//----------------------------------------------------------------------------------
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// Function: lpc47n227_pnp_set_iobase
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// Parameters: dev - high 8 bits = Super I/O port,
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// low 8 bits = logical device number (per lpc47n227.h)
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// iobase - base I/O port for the logical device
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// Return Value: None
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// Description: Program the base I/O port for the specified logical device.
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//
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void lpc47n227_pnp_set_iobase(device_t dev, unsigned iobase)
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{
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// LPC47N227 requires base ports to be a multiple of 4
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ASSERT(!(iobase & 0x3));
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switch (dev & 0xFF) {
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case LPC47N227_PP:
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pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
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break;
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case LPC47N227_SP1:
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pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
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break;
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case LPC47N227_SP2:
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pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
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break;
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default:
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break;
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}
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}
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//----------------------------------------------------------------------------------
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// Function: lpc47n227_pnp_set_enable
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// Parameters: dev - high 8 bits = Super I/O port,
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// low 8 bits = logical device number (per lpc47n227.h)
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// enable - 0 to disable, anythig else to enable
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// Return Value: None
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// Description: Enable or disable the specified logical device.
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// Technically, a full disable requires setting the device's base
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// I/O port below 0x100. We don't do that here, because we don't
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// have access to a data structure that specifies what the 'real'
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// base port is (when asked to enable the device). Also the function
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// is used only to disable the device while its true base port is
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// programmed (see lpc47n227_enable_serial() below).
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//
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void lpc47n227_pnp_set_enable(device_t dev, int enable)
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{
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uint8_t power_register = 0;
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uint8_t power_mask = 0;
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uint8_t current_power;
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uint8_t new_power;
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switch (dev & 0xFF) {
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case LPC47N227_PP:
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power_register = 0x01;
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power_mask = 0x04;
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break;
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case LPC47N227_SP1:
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power_register = 0x02;
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power_mask = 0x08;
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break;
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case LPC47N227_SP2:
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power_register = 0x02;
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power_mask = 0x80;
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break;
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default:
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return;
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}
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current_power = pnp_read_config(dev, power_register);
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new_power = current_power & ~power_mask; // disable by default
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if (enable)
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new_power |= power_mask; // Enable
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pnp_write_config(dev, power_register, new_power);
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}
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//----------------------------------------------------------------------------------
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// Function: lpc47n227_enable_serial
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// Parameters: dev - high 8 bits = Super I/O port,
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// low 8 bits = logical device number (per lpc47n227.h)
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// iobase - processor I/O port address to assign to this serial device
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// Return Value: bool
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// Description: Configure the base I/O port of the specified serial device
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// and enable the serial device.
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//
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static void lpc47n227_enable_serial(device_t dev, unsigned iobase)
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{
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// NOTE: Cannot use pnp_set_XXX() here because they assume chip
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// support for logical devices, which the LPC47N227 doesn't have
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pnp_enter_conf_state(dev);
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lpc47n227_pnp_set_enable(dev, 0);
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lpc47n227_pnp_set_iobase(dev, iobase);
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lpc47n227_pnp_set_enable(dev, 1);
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pnp_exit_conf_state(dev);
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}
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@ -0,0 +1,352 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2005 Digital Design Corporation
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* RAM-based driver for SMSC LPC47N227 Super I/O chip. */
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pnp.h>
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#include <console/console.h>
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#include <device/smbus.h>
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#include <string.h>
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#include <bitops.h>
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#include <uart8250.h>
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#include <assert.h>
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#include <stdlib.h>
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#include "chip.h"
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#include "lpc47n227.h"
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// Forward declarations
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static void enable_dev(device_t dev);
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void lpc47n227_pnp_set_resources(device_t dev);
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void lpc47n227_pnp_enable_resources(device_t dev);
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void lpc47n227_pnp_enable(device_t dev);
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static void lpc47n227_init(device_t dev);
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static void lpc47n227_pnp_set_resource(device_t dev, struct resource *resource);
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void lpc47n227_pnp_set_iobase(device_t dev, unsigned iobase);
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void lpc47n227_pnp_set_drq(device_t dev, unsigned drq);
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void lpc47n227_pnp_set_irq(device_t dev, unsigned irq);
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void lpc47n227_pnp_set_enable(device_t dev, int enable);
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static void pnp_enter_conf_state(device_t dev);
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static void pnp_exit_conf_state(device_t dev);
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struct chip_operations superio_smsc_lpc47n227_ops = {
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CHIP_NAME("SMSC LPC47N227 Super I/O")
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.enable_dev = enable_dev,
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};
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static struct device_operations ops = {
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.read_resources = pnp_read_resources,
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.set_resources = lpc47n227_pnp_set_resources,
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.enable_resources = lpc47n227_pnp_enable_resources,
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.enable = lpc47n227_pnp_enable,
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.init = lpc47n227_init,
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};
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static struct pnp_info pnp_dev_info[] = {
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{&ops, LPC47N227_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
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{&ops, LPC47N227_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
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{&ops, LPC47N227_SP2, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
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{&ops, LPC47N227_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0},
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{0x7f8, 0x4},}
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};
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/**********************************************************************************/
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/* PUBLIC INTERFACE */
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/**********************************************************************************/
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//----------------------------------------------------------------------------------
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// Function: enable_dev
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// Parameters: dev - pointer to structure describing a Super I/O device
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// Return Value: None
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// Description: Create device structures and allocate resources to devices
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// specified in the pnp_dev_info array (above).
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//
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static void enable_dev(device_t dev)
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{
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pnp_enable_devices(dev, &pnp_ops,
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ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
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}
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//----------------------------------------------------------------------------------
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// Function: lpc47n227_pnp_set_resources
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// Parameters: dev - pointer to structure describing a Super I/O device
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// Return Value: None
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// Description: Configure the specified Super I/O device with the resources
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// (I/O space, etc.) that have been allocate for it.
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//
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void lpc47n227_pnp_set_resources(device_t dev)
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{
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int i;
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pnp_enter_conf_state(dev);
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// NOTE: Cannot use pnp_set_resources() here because it assumes chip
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// support for logical devices, which the LPC47N227 doesn't have
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for (i = 0; i < dev->resources; i++)
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lpc47n227_pnp_set_resource(dev, &dev->resource[i]);
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pnp_exit_conf_state(dev);
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}
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void lpc47n227_pnp_enable_resources(device_t dev)
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{
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pnp_enter_conf_state(dev);
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// NOTE: Cannot use pnp_enable_resources() here because it assumes chip
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// support for logical devices, which the LPC47N227 doesn't have
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lpc47n227_pnp_set_enable(dev, 1);
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pnp_exit_conf_state(dev);
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}
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void lpc47n227_pnp_enable(device_t dev)
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{
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pnp_enter_conf_state(dev);
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// NOTE: Cannot use pnp_set_enable() here because it assumes chip
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// support for logical devices, which the LPC47N227 doesn't have
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if (dev->enabled) {
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lpc47n227_pnp_set_enable(dev, 1);
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} else {
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lpc47n227_pnp_set_enable(dev, 0);
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}
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pnp_exit_conf_state(dev);
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}
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//----------------------------------------------------------------------------------
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// Function: lpc47n227_init
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// Parameters: dev - pointer to structure describing a Super I/O device
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// Return Value: None
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// Description: Initialize the specified Super I/O device.
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// Devices other than COM ports and keyboard controller are ignored.
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// For COM ports, we configure the baud rate.
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//
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static void lpc47n227_init(device_t dev)
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{
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struct superio_smsc_lpc47n227_config *conf = dev->chip_info;
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struct resource *res0;
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if (!dev->enabled)
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return;
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switch (dev->path.pnp.device) {
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case LPC47N227_SP1:
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res0 = find_resource(dev, PNP_IDX_IO0);
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init_uart8250(res0->base, &conf->com1);
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break;
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case LPC47N227_SP2:
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res0 = find_resource(dev, PNP_IDX_IO0);
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init_uart8250(res0->base, &conf->com2);
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break;
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case LPC47N227_KBDC:
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printk_debug("LPC47N227: Initializing keyboard.\n");
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init_pc_keyboard(0x60, 0x64, &conf->keyboard);
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break;
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}
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}
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/**********************************************************************************/
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/* PRIVATE FUNCTIONS */
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/**********************************************************************************/
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static void lpc47n227_pnp_set_resource(device_t dev, struct resource *resource)
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{
|
||||
if (!(resource->flags & IORESOURCE_ASSIGNED)) {
|
||||
printk_err("ERROR: %s %02lx not allocated\n",
|
||||
dev_path(dev), resource->index);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Now store the resource */
|
||||
// NOTE: Cannot use pnp_set_XXX() here because they assume chip
|
||||
// support for logical devices, which the LPC47N227 doesn't have
|
||||
|
||||
if (resource->flags & IORESOURCE_IO) {
|
||||
lpc47n227_pnp_set_iobase(dev, resource->base);
|
||||
} else if (resource->flags & IORESOURCE_DRQ) {
|
||||
lpc47n227_pnp_set_drq(dev, resource->base);
|
||||
} else if (resource->flags & IORESOURCE_IRQ) {
|
||||
lpc47n227_pnp_set_irq(dev, resource->base);
|
||||
} else {
|
||||
printk_err("ERROR: %s %02lx unknown resource type\n",
|
||||
dev_path(dev), resource->index);
|
||||
return;
|
||||
}
|
||||
resource->flags |= IORESOURCE_STORED;
|
||||
|
||||
report_resource_stored(dev, resource, "");
|
||||
}
|
||||
|
||||
void lpc47n227_pnp_set_iobase(device_t dev, unsigned iobase)
|
||||
{
|
||||
ASSERT(!(iobase & 0x3));
|
||||
|
||||
switch (dev->path.pnp.device) {
|
||||
case LPC47N227_PP:
|
||||
pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
|
||||
break;
|
||||
|
||||
case LPC47N227_SP1:
|
||||
pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
|
||||
break;
|
||||
|
||||
case LPC47N227_SP2:
|
||||
pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
|
||||
break;
|
||||
|
||||
case LPC47N227_KBDC:
|
||||
break;
|
||||
|
||||
default:
|
||||
BUG();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void lpc47n227_pnp_set_drq(device_t dev, unsigned drq)
|
||||
{
|
||||
if (dev->path.pnp.device == LPC47N227_PP) {
|
||||
const uint8_t PP_DMA_MASK = 0x0F;
|
||||
const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;
|
||||
uint8_t current_config =
|
||||
pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);
|
||||
uint8_t new_config;
|
||||
|
||||
ASSERT(!(drq & ~PP_DMA_MASK)); // DRQ out of range??
|
||||
new_config = (current_config & ~PP_DMA_MASK) | drq;
|
||||
pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
|
||||
} else {
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
void lpc47n227_pnp_set_irq(device_t dev, unsigned irq)
|
||||
{
|
||||
uint8_t irq_config_register = 0;
|
||||
uint8_t irq_config_mask = 0;
|
||||
uint8_t current_config;
|
||||
uint8_t new_config;
|
||||
|
||||
switch (dev->path.pnp.device) {
|
||||
case LPC47N227_PP:
|
||||
irq_config_register = 0x27;
|
||||
irq_config_mask = 0x0F;
|
||||
break;
|
||||
|
||||
case LPC47N227_SP1:
|
||||
irq_config_register = 0x28;
|
||||
irq_config_mask = 0xF0;
|
||||
irq <<= 4;
|
||||
break;
|
||||
|
||||
case LPC47N227_SP2:
|
||||
irq_config_register = 0x28;
|
||||
irq_config_mask = 0x0F;
|
||||
break;
|
||||
|
||||
case LPC47N227_KBDC:
|
||||
break;
|
||||
|
||||
default:
|
||||
BUG();
|
||||
return;
|
||||
}
|
||||
|
||||
current_config = pnp_read_config(dev, irq_config_register);
|
||||
new_config = (current_config & ~irq_config_mask) | irq;
|
||||
pnp_write_config(dev, irq_config_register, new_config);
|
||||
}
|
||||
|
||||
void lpc47n227_pnp_set_enable(device_t dev, int enable)
|
||||
{
|
||||
uint8_t power_register = 0;
|
||||
uint8_t power_mask = 0;
|
||||
uint8_t current_power;
|
||||
uint8_t new_power;
|
||||
|
||||
switch (dev->path.pnp.device) {
|
||||
case LPC47N227_PP:
|
||||
power_register = 0x01;
|
||||
power_mask = 0x04;
|
||||
break;
|
||||
|
||||
case LPC47N227_SP1:
|
||||
power_register = 0x02;
|
||||
power_mask = 0x08;
|
||||
break;
|
||||
|
||||
case LPC47N227_SP2:
|
||||
power_register = 0x02;
|
||||
power_mask = 0x80;
|
||||
break;
|
||||
|
||||
case LPC47N227_KBDC:
|
||||
break;
|
||||
|
||||
default:
|
||||
BUG();
|
||||
return;
|
||||
}
|
||||
|
||||
current_power = pnp_read_config(dev, power_register);
|
||||
new_power = current_power & ~power_mask; // disable by default
|
||||
|
||||
if (enable) {
|
||||
struct resource *ioport_resource =
|
||||
find_resource(dev, PNP_IDX_IO0);
|
||||
lpc47n227_pnp_set_iobase(dev, ioport_resource->base);
|
||||
|
||||
new_power |= power_mask; // Enable
|
||||
|
||||
} else {
|
||||
lpc47n227_pnp_set_iobase(dev, 0);
|
||||
}
|
||||
pnp_write_config(dev, power_register, new_power);
|
||||
}
|
||||
|
||||
//----------------------------------------------------------------------------------
|
||||
// Function: pnp_enter_conf_state
|
||||
// Parameters: dev - pointer to structure describing a Super I/O device
|
||||
// Return Value: None
|
||||
// Description: Enable access to the LPC47N227's configuration registers.
|
||||
//
|
||||
static void pnp_enter_conf_state(device_t dev)
|
||||
{
|
||||
outb(0x55, dev->path.pnp.port);
|
||||
}
|
||||
|
||||
//----------------------------------------------------------------------------------
|
||||
// Function: pnp_exit_conf_state
|
||||
// Parameters: dev - pointer to structure describing a Super I/O device
|
||||
// Return Value: None
|
||||
// Description: Disable access to the LPC47N227's configuration registers.
|
||||
//
|
||||
static void pnp_exit_conf_state(device_t dev)
|
||||
{
|
||||
outb(0xaa, dev->path.pnp.port);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue