mb/google/poppy/variants/nautilus: add nautilus board
Create Nautilus board which derives from Poppy, a KBL reference board. BRANCH=master BUG=b:66462881 TEST=Build (as initial setup) Change-Id: I6ca5ab821a7ba1746b37dfd3ea1ed367094d4f52 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/21895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Chris Wang
Furquan Shaikh
parent
8ce7bc18fa
commit
5547c371c1
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@ -5,7 +5,8 @@ config BOARD_GOOGLE_BASEBOARD_POPPY
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select DRIVERS_I2C_MAX98927
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select DRIVERS_I2C_MAX98927 if !BOARD_GOOGLE_NAUTILUS
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select DRIVERS_PS2_KEYBOARD if BOARD_GOOGLE_NAUTILUS
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select DRIVERS_SPI_ACPI
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_BOARDID
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@ -14,7 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_POPPY
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select HAVE_ACPI_TABLES
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_USES_FSP2_0
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select NO_FADT_8042
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select NO_FADT_8042 if !BOARD_GOOGLE_NAUTILUS
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select POPPY_USE_I2C_TPM if !VBOOT_MOCK_SECDATA
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select SOC_INTEL_KABYLAKE
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@ -22,6 +23,7 @@ if BOARD_GOOGLE_BASEBOARD_POPPY
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config DEVICETREE
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string
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default "variants/nautilus/devicetree.cb" if BOARD_GOOGLE_NAUTILUS
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default "variants/soraka/devicetree.cb" if BOARD_GOOGLE_SORAKA
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default "variants/baseboard/devicetree.cb"
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@ -41,6 +43,7 @@ config GBB_HWID
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string
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depends on CHROMEOS
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default "POPPY TEST 8294" if BOARD_GOOGLE_POPPY
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default "NAUTILUS TEST 3013" if BOARD_GOOGLE_NAUTILUS
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default "SORAKA TEST 1869" if BOARD_GOOGLE_SORAKA
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config INCLUDE_NHLT_BLOBS
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@ -50,6 +53,11 @@ config INCLUDE_NHLT_BLOBS
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select NHLT_MAX98927
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select NHLT_RT5663
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config INCLUDE_NHLT_BLOBS_NAUTILUS
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bool "Include blobs for nautilus audio."
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select NHLT_DMIC_2CH
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select NHLT_DMIC_4CH
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config MAINBOARD_DIR
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string
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default "google/poppy"
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@ -57,11 +65,13 @@ config MAINBOARD_DIR
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config MAINBOARD_FAMILY
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string
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default "Google_Poppy" if BOARD_GOOGLE_POPPY
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default "Google_Nautilus" if BOARD_GOOGLE_NAUTILUS
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default "Google_Soraka" if BOARD_GOOGLE_SORAKA
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config MAINBOARD_PART_NUMBER
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string
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default "Poppy" if BOARD_GOOGLE_POPPY
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default "Nautilus" if BOARD_GOOGLE_NAUTILUS
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default "Soraka" if BOARD_GOOGLE_SORAKA
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config MAX_CPUS
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@ -92,6 +102,7 @@ config TPM_TIS_ACPI_INTERRUPT
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config VARIANT_DIR
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string
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default "poppy" if BOARD_GOOGLE_POPPY
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default "nautilus" if BOARD_GOOGLE_NAUTILUS
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default "soraka" if BOARD_GOOGLE_SORAKA
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config VBOOT
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@ -2,6 +2,10 @@ config BOARD_GOOGLE_POPPY
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bool "Poppy"
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select BOARD_GOOGLE_BASEBOARD_POPPY
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config BOARD_GOOGLE_NAUTILUS
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bool "Nautilus"
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select BOARD_GOOGLE_BASEBOARD_POPPY
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config BOARD_GOOGLE_SORAKA
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bool "Soraka"
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select BOARD_GOOGLE_BASEBOARD_POPPY
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@ -0,0 +1,5 @@
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SPD_SOURCES = empty # 0b0000
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bootblock-y += gpio.c
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ramstage-y += gpio.c
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@ -0,0 +1,282 @@
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chip soc/intel/skylake
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# Deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "1"
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register "deep_s5_enable_ac" = "1"
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register "deep_s5_enable_dc" = "1"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "GPP_B"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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# Enable DPTF
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register "dptf_enable" = "1"
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# Enable S0ix
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register "s0ix_enable" = "1"
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# FSP Configuration
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register "ProbelessTrace" = "0"
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register "EnableLan" = "0"
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register "EnableSata" = "0"
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register "SataSalpSupport" = "0"
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register "SataMode" = "0"
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register "SataPortsEnable[0]" = "0"
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register "EnableAzalia" = "1"
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "EnableTraceHub" = "0"
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register "XdciEnable" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "1"
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register "SaImguEnable" = "1"
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register "ScsEmmcEnabled" = "1"
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register "ScsEmmcHs400Enabled" = "1"
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register "ScsSdCardEnabled" = "2"
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register "IshEnable" = "0"
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register "PttSwitch" = "0"
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register "InternalGfx" = "1"
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register "SkipExtGfxScan" = "1"
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register "Device4Enable" = "1"
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register "HeciEnabled" = "0"
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register "FspSkipMpInit" = "1"
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register "SaGv" = "3"
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register "SerialIrqConfigSirqEnable" = "1"
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register "PmConfigSlpS3MinAssert" = "2" # 50ms
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register "PmConfigSlpS4MinAssert" = "1" # 1s
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register "PmConfigSlpSusMinAssert" = "1" # 500ms
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmTimerDisabled" = "1"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqc_routing" = "PCH_IRQ11"
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register "pirqd_routing" = "PCH_IRQ11"
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register "pirqe_routing" = "PCH_IRQ11"
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register "pirqf_routing" = "PCH_IRQ11"
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register "pirqg_routing" = "PCH_IRQ11"
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register "pirqh_routing" = "PCH_IRQ11"
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# VR Settings Configuration for 4 Domains
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#+----------------+-------+-------+-------+-------+
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#| Domain/Setting | SA | IA | GTUS | GTS |
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#+----------------+-------+-------+-------+-------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 2A | 2A | 2A | 2A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 |
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#| IccMax | 5A | 24A | 24A | 24A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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#| AcLoadline | 15 | 5.7 | 5.5 | 5.5 |
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#| DcLoadline | 14.3 | 4.83 | 4.2 | 4.2 |
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#+----------------+-------+-------+-------+-------+
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(2),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(5),
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.voltage_limit = 1520,
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.ac_loadline = 1500,
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.dc_loadline = 1430,
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(2),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(24),
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.voltage_limit = 1520,
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.ac_loadline = 570,
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.dc_loadline = 483,
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(2),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(24),
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.voltage_limit = 1520,
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.ac_loadline = 550,
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.dc_loadline = 420,
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(2),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(24),
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.voltage_limit = 1520,
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.ac_loadline = 550,
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.dc_loadline = 420,
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}"
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# Enable Root port 1.
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register "PcieRpEnable[0]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[0]" = "1"
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# RP 1 uses SRCCLKREQ1#
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register "PcieRpClkReqNumber[0]" = "1"
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register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
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register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
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register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port
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register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
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# Touchscreen
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register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
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# H1
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register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"
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# Configure I2C1 for cr50 TPM. Early init is required to set up a BAR
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# for TPM communication before memory is up.
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register "i2c[1]" = "{
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.early_init = 1,
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}"
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# Trackpad
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register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"
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# Pen
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register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"
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# Camera
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register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
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# Audio
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register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8"
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# Must leave UART0 enabled or SD/eMMC will not work as PCI
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoPci,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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[PchSerialIoIndexSpi0] = PchSerialIoDisabled,
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[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
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[PchSerialIoIndexUart0] = PchSerialIoPci,
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[PchSerialIoIndexUart1] = PchSerialIoDisabled,
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
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}"
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register "speed_shift_enable" = "1"
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# PL2 override 15W for KBL-Y
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register "tdp_pl2_override" = "15"
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register "tcc_offset" = "10" # TCC of 90C
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# Use default SD card detect GPIO configuration
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register "sdcard_cd_gpio_default" = "GPP_E15"
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# Lock Down
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register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 14.0 on end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 15.0 on end # I2C #0
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device pci 15.1 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
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device i2c 50 on end
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end
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end # I2C #1
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device pci 15.2 on end # I2C #2
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device pci 15.3 on end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 off end # SATA
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device pci 19.0 on end # UART #2
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device pci 19.1 on end # I2C #5
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device pci 19.2 on end # I2C #4
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device pci 1c.0 on
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chip drivers/intel/wifi
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register "wake" = "GPE0_PCI_EXP"
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device pci 00.0 on end
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end
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end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 off end # PCI Express Port 5
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 off end # PCI Express Port 9
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1e.0 on end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1e.4 on end # eMMC
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device pci 1e.5 off end # SDIO
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device pci 1e.6 on end # SDCard
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device pci 1f.0 on
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end # LPC Interface
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device pci 1f.1 on end # P2SB
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 on end # Intel HDA
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE
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end
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end
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@ -0,0 +1,427 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2017 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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/* Pad configuration in ramstage */
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/* Leave eSPI pins untouched from default settings */
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static const struct pad_config gpio_table[] = {
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/* A0 : RCIN# ==> NC(TP41) */
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PAD_CFG_NC(GPP_A0),
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/* A1 : ESPI_IO0 */
|
||||
/* A2 : ESPI_IO1 */
|
||||
/* A3 : ESPI_IO2 */
|
||||
/* A4 : ESPI_IO3 */
|
||||
/* A5 : ESPI_CS# */
|
||||
/* A6 : SERIRQ ==> NC(TP44) */
|
||||
PAD_CFG_NC(GPP_A6),
|
||||
/* A7 : PIRQA# ==> NC(TP29) */
|
||||
PAD_CFG_NC(GPP_A7),
|
||||
/* A8 : CLKRUN# ==> NC(TP45) */
|
||||
PAD_CFG_NC(GPP_A8),
|
||||
/* A9 : ESPI_CLK */
|
||||
/* A10 : CLKOUT_LPC1 ==> NC */
|
||||
PAD_CFG_NC(GPP_A10),
|
||||
/* A11 : PME# ==> NC(TP67) */
|
||||
PAD_CFG_NC(GPP_A11),
|
||||
/* A12 : BM_BUSY# ==> NC */
|
||||
PAD_CFG_NC(GPP_A12),
|
||||
/* A13 : SUSWARN# ==> SUSWARN_L */
|
||||
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
/* A14 : ESPI_RESET# */
|
||||
/* A15 : SUSACK# ==> SUSACK_L */
|
||||
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
|
||||
/* A16 : SD_1P8_SEL ==> SD_PWR_1800_SEL */
|
||||
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
/* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */
|
||||
PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
|
||||
/* A18 : ISH_GP0 ==> NC */
|
||||
PAD_CFG_NC(GPP_A18),
|
||||
/* A19 : ISH_GP1 ==> NC */
|
||||
PAD_CFG_NC(GPP_A19),
|
||||
/* A20 : ISH_GP2 ==> ACCEL_GYRO_INT_L */
|
||||
PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST),
|
||||
/* A21 : ISH_GP3 ==> NC */
|
||||
PAD_CFG_NC(GPP_A21),
|
||||
/* A22 : ISH_GP4 ==> NC */
|
||||
PAD_CFG_NC(GPP_A22),
|
||||
/* A23 : ISH_GP5 ==> NC */
|
||||
PAD_CFG_NC(GPP_A23),
|
||||
|
||||
/* B0 : CORE_VID0 ==> NC(TP42) */
|
||||
PAD_CFG_NC(GPP_B0),
|
||||
/* B1 : CORE_VID1 ==> NC(TP43) */
|
||||
PAD_CFG_NC(GPP_B1),
|
||||
/* B2 : VRALERT# ==> NC */
|
||||
PAD_CFG_NC(GPP_B2),
|
||||
/* B3 : CPU_GP2 ==> NC */
|
||||
PAD_CFG_NC(GPP_B3),
|
||||
/* B4 : CPU_GP3 ==> NC */
|
||||
PAD_CFG_NC(GPP_B4),
|
||||
/* B5 : SRCCLKREQ0# ==> NC */
|
||||
PAD_CFG_NC(GPP_B5),
|
||||
/* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */
|
||||
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
|
||||
/* B7 : SRCCLKREQ2# ==> NC */
|
||||
PAD_CFG_NC(GPP_B7),
|
||||
/* B9 : SRCCLKREQ4# ==> NC */
|
||||
PAD_CFG_NC(GPP_B9),
|
||||
/* B10 : SRCCLKREQ5# ==> NC */
|
||||
PAD_CFG_NC(GPP_B10),
|
||||
/* B11 : EXT_PWR_GATE# ==> NC */
|
||||
PAD_CFG_NC(GPP_B11),
|
||||
/* B12 : SLP_S0# ==> SLP_S0_L_G */
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
/* B13 : PLTRST# ==> PLT_RST_L */
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
/* B14 : SPKR ==> NC */
|
||||
PAD_CFG_NC(GPP_B14),
|
||||
#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)
|
||||
/* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */
|
||||
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
|
||||
/* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */
|
||||
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
|
||||
/* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */
|
||||
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
|
||||
/* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */
|
||||
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
|
||||
#else
|
||||
/* B15 : GSPI0_CS# ==> NC */
|
||||
PAD_CFG_NC(GPP_B15),
|
||||
/* B16 : GSPI0_CLK ==> NC */
|
||||
PAD_CFG_NC(GPP_B16),
|
||||
/* B17 : GSPI0_MISO ==> NC */
|
||||
PAD_CFG_NC(GPP_B17),
|
||||
/* B18 : GSPI0_MOSI ==> NC */
|
||||
PAD_CFG_NC(GPP_B18),
|
||||
#endif
|
||||
/* B19 : GSPI1_CS# ==> NC */
|
||||
PAD_CFG_NC(GPP_B19),
|
||||
/* B20 : GSPI1_CLK ==> NC */
|
||||
PAD_CFG_NC(GPP_B20),
|
||||
/* B21 : GSPI1_MISO ==> NC */
|
||||
PAD_CFG_NC(GPP_B21),
|
||||
/* B22 : GSPI1_MOSI ==> NC */
|
||||
PAD_CFG_NC(GPP_B22),
|
||||
/* B23 : SM1ALERT# ==> NC */
|
||||
PAD_CFG_NC(GPP_B23),
|
||||
|
||||
/* C0 : SMBCLK ==> NC */
|
||||
PAD_CFG_NC(GPP_C0),
|
||||
/* C1 : SMBDATA ==> NC */
|
||||
PAD_CFG_NC(GPP_C1),
|
||||
/* C2 : SMBALERT# ==> NC */
|
||||
PAD_CFG_NC(GPP_C2),
|
||||
/* C3 : SML0CLK ==> NC */
|
||||
PAD_CFG_NC(GPP_C3),
|
||||
/* C4 : SML0DATA ==> NC */
|
||||
PAD_CFG_NC(GPP_C4),
|
||||
/* C5 : SML0ALERT# ==> NC */
|
||||
PAD_CFG_NC(GPP_C5),
|
||||
/* C6 : SM1CLK ==> EC_IN_RW_OD */
|
||||
PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP),
|
||||
/* C7 : SM1DATA ==> NC */
|
||||
PAD_CFG_NC(GPP_C7),
|
||||
/* C8 : UART0_RXD ==> FP_INT */
|
||||
PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST),
|
||||
/* C9 : UART0_TXD ==> FP_RST_ODL */
|
||||
PAD_CFG_GPO(GPP_C9, 0, DEEP),
|
||||
/* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */
|
||||
PAD_CFG_GPO(GPP_C10, 1, DEEP),
|
||||
/* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */
|
||||
PAD_CFG_GPO(GPP_C11, 1, DEEP),
|
||||
/* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */
|
||||
PAD_CFG_GPI(GPP_C12, NONE, DEEP),
|
||||
/* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */
|
||||
PAD_CFG_GPI(GPP_C13, NONE, DEEP),
|
||||
/* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */
|
||||
PAD_CFG_GPI(GPP_C14, NONE, DEEP),
|
||||
/* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */
|
||||
PAD_CFG_GPI(GPP_C15, NONE, DEEP),
|
||||
/* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_3V3_SDA */
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
/* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM)
|
||||
/* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
/* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
#else
|
||||
/* C18 : I2C1_SDA ==> NC */
|
||||
PAD_CFG_NC(GPP_C18),
|
||||
/* C19 : I2C1_SCL ==> NC */
|
||||
PAD_CFG_NC(GPP_C19),
|
||||
#endif
|
||||
/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
|
||||
/* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
|
||||
/* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */
|
||||
PAD_CFG_GPO(GPP_C22, 0, DEEP),
|
||||
/* C23 : UART2_CTS# ==> PCH_WP */
|
||||
PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
|
||||
|
||||
/* D0 : SPI1_CS# ==> NC */
|
||||
PAD_CFG_NC(GPP_D0),
|
||||
/* D1 : SPI1_CLK ==> NC */
|
||||
PAD_CFG_NC(GPP_D1),
|
||||
/* D2 : SPI1_MISO ==> NC */
|
||||
PAD_CFG_NC(GPP_D2),
|
||||
/* D3 : SPI1_MOSI ==> NC */
|
||||
PAD_CFG_NC(GPP_D3),
|
||||
/* D4 : FASHTRIG ==> NC */
|
||||
PAD_CFG_NC(GPP_D4),
|
||||
/* D5 : ISH_I2C0_SDA ==> ISH_I2C_SENSOR_1V8_SDA */
|
||||
PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1),
|
||||
/* D6 : ISH_I2C0_SCL ==> ISH_I2C_SENSOR_1V8_SCL */
|
||||
PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1),
|
||||
/* D7 : ISH_I2C1_SDA ==> NC */
|
||||
PAD_CFG_NC(GPP_D7),
|
||||
/* D8 : ISH_I2C1_SCL ==> NC */
|
||||
PAD_CFG_NC(GPP_D8),
|
||||
/* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */
|
||||
PAD_CFG_GPI(GPP_D9, NONE, PLTRST),
|
||||
/* D10 : ISH_SPI_CLK ==> SPKR_RST_L */
|
||||
PAD_CFG_GPO(GPP_D10, 1, DEEP),
|
||||
/* D11 : ISH_SPI_MISO ==> SPKR_INT_L */
|
||||
PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST),
|
||||
/* D12 : ISH_SPI_MOSI ==> NC */
|
||||
PAD_CFG_NC(GPP_D12),
|
||||
/* D13 : ISH_UART0_RXD ==> NC */
|
||||
PAD_CFG_NC(GPP_D13),
|
||||
/* D14 : ISH_UART0_TXD ==> NC */
|
||||
PAD_CFG_NC(GPP_D14),
|
||||
/* D15 : ISH_UART0_RTS# ==> NC */
|
||||
PAD_CFG_NC(GPP_D15),
|
||||
/* D16 : ISH_UART0_CTS# ==> NC */
|
||||
PAD_CFG_NC(GPP_D16),
|
||||
/* D17 : DMIC_CLK1 */
|
||||
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
|
||||
/* D18 : DMIC_DATA1 */
|
||||
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
|
||||
/* D19 : DMIC_CLK0 */
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
/* D20 : DMIC_DATA0 */
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
/* D21 : SPI1_IO2 ==> NC */
|
||||
PAD_CFG_NC(GPP_D21),
|
||||
/* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */
|
||||
PAD_CFG_GPO(GPP_D22, 1, DEEP),
|
||||
/* D23 : I2S_MCLK ==> I2S_MCLK_R */
|
||||
PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
|
||||
|
||||
/* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
|
||||
PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
|
||||
/* E1 : SATAXPCIE1 ==> NC */
|
||||
PAD_CFG_NC(GPP_E1),
|
||||
/* E2 : SATAXPCIE2 ==> NC */
|
||||
PAD_CFG_NC(GPP_E2),
|
||||
/* E3 : CPU_GP0 ==> TOUCHSCREEN_RST_L */
|
||||
PAD_CFG_GPO(GPP_E3, 0, DEEP),
|
||||
/* E4 : SATA_DEVSLP0 ==> NC */
|
||||
PAD_CFG_NC(GPP_E4),
|
||||
/* E5 : SATA_DEVSLP1 ==> NC */
|
||||
PAD_CFG_NC(GPP_E5),
|
||||
/* E6 : SATA_DEVSLP2 ==> NC */
|
||||
PAD_CFG_NC(GPP_E6),
|
||||
/* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */
|
||||
PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),
|
||||
/* E8 : SATALED# ==> NC */
|
||||
PAD_CFG_NC(GPP_E8),
|
||||
/* E9 : USB2_OCO# ==> USB_C0_OC_ODL */
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
/* E10 : USB2_OC1# ==> USB_C1_OC_ODL */
|
||||
PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
|
||||
/* E11 : USB2_OC2# ==> TOUCHSCREEN_STOP_L */
|
||||
PAD_CFG_GPO(GPP_E11, 0, DEEP),
|
||||
/* E12 : USB2_OC3# ==> USB2_OC3_L */
|
||||
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
|
||||
/* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */
|
||||
PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1),
|
||||
/* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */
|
||||
PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),
|
||||
/* E15 : DDPD_HPD2 ==> SD_CD# */
|
||||
PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP),
|
||||
/* E16 : DDPE_HPD3 ==> NC(TP244) */
|
||||
PAD_CFG_NC(GPP_E16),
|
||||
/* E17 : EDP_HPD */
|
||||
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||
/* E18 : DDPB_CTRLCLK ==> NC */
|
||||
PAD_CFG_NC(GPP_E18),
|
||||
/* E19 : DDPB_CTRLDATA ==> NC */
|
||||
PAD_CFG_NC(GPP_E19),
|
||||
/* E20 : DDPC_CTRLCLK ==> NC */
|
||||
PAD_CFG_NC(GPP_E20),
|
||||
/* E21 : DDPC_CTRLDATA ==> NC */
|
||||
PAD_CFG_NC(GPP_E21),
|
||||
/* E22 : DDPD_CTRLCLK ==> NC */
|
||||
PAD_CFG_NC(GPP_E22),
|
||||
/* E23 : DDPD_CTRLDATA ==> NC */
|
||||
PAD_CFG_NC(GPP_E23),
|
||||
|
||||
/* The next 4 pads are for bit banging the amplifiers, default to I2S */
|
||||
/* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */
|
||||
PAD_CFG_GPI(GPP_F0, NONE, DEEP),
|
||||
/* F1 : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */
|
||||
PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
||||
/* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */
|
||||
PAD_CFG_GPI(GPP_F2, NONE, DEEP),
|
||||
/* F3 : I2S2_RXD */
|
||||
PAD_CFG_GPI(GPP_F3, NONE, DEEP),
|
||||
/* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */
|
||||
PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),
|
||||
/* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */
|
||||
PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1),
|
||||
/* F6 : I2C3_SDA ==> PCH_I2C3_PEN_1V8_SDA */
|
||||
PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1),
|
||||
/* F7 : I2C3_SCL ==> PCH_I2C3_PEN_1V8_SCL */
|
||||
PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1),
|
||||
/* F8 : I2C4_SDA ==> PCH_I2C4_UFCAM_1V8_SDA */
|
||||
PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
|
||||
/* F9 : I2C4_SCL ==> PCH_I2C4_UFCAM_1V8_SCL */
|
||||
PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
|
||||
/* F10 : I2C5_SDA ==> PCH_I2C5_AUDIO_1V8_SDA */
|
||||
PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1),
|
||||
/* F11 : I2C5_SCL ==> PCH_I2C5_AUDIO_1V8_SCL */
|
||||
PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1),
|
||||
/* F12 : EMMC_CMD */
|
||||
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
|
||||
/* F13 : EMMC_DATA0 */
|
||||
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
|
||||
/* F14 : EMMC_DATA1 */
|
||||
PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
|
||||
/* F15 : EMMC_DATA2 */
|
||||
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
|
||||
/* F16 : EMMC_DATA3 */
|
||||
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
|
||||
/* F17 : EMMC_DATA4 */
|
||||
PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
|
||||
/* F18 : EMMC_DATA5 */
|
||||
PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
|
||||
/* F19 : EMMC_DATA6 */
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
/* F20 : EMMC_DATA7 */
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
/* F21 : EMMC_RCLK */
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
/* F22 : EMMC_CLK */
|
||||
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
|
||||
/* F23 : RSVD ==> NC */
|
||||
PAD_CFG_NC(GPP_F23),
|
||||
|
||||
/* G0 : SD_CMD */
|
||||
PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
|
||||
/* G1 : SD_DATA0 */
|
||||
PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
|
||||
/* G2 : SD_DATA1 */
|
||||
PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
|
||||
/* G3 : SD_DATA2 */
|
||||
PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
|
||||
/* G4 : SD_DATA3 */
|
||||
PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
|
||||
/* G5 : SD_CD# */
|
||||
PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
|
||||
/* G6 : SD_CLK */
|
||||
PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
|
||||
/* G7 : SD_WP */
|
||||
PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1),
|
||||
|
||||
/* GPD0: BATLOW# ==> PCH_BATLOW_L */
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
/* GPD1: ACPRESENT ==> EC_PCH_ACPRESENT */
|
||||
PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
||||
/* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */
|
||||
PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
|
||||
/* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */
|
||||
PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
|
||||
/* GPD4: SLP_S3# ==> SLP_S3_L */
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
/* GPD5: SLP_S4# ==> SLP_S4_L */
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
/* GPD6: SLP_A# ==> NC(TP26) */
|
||||
PAD_CFG_NC(GPD6),
|
||||
/* GPD7: RSVD ==> NC */
|
||||
PAD_CFG_NC(GPD7),
|
||||
/* GPD8: SUSCLK ==> PCH_SUSCLK */
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* GPD9: SLP_WLAN# ==> NC(TP25) */
|
||||
PAD_CFG_NC(GPD9),
|
||||
/* GPD10: SLP_S5# ==> NC(TP15) */
|
||||
PAD_CFG_NC(GPD10),
|
||||
/* GPD11: LANPHYC ==> NC */
|
||||
PAD_CFG_NC(GPD11),
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */
|
||||
PAD_CFG_GPO(GPP_B8, 0, DEEP),
|
||||
|
||||
#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)
|
||||
/* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */
|
||||
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
|
||||
/* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */
|
||||
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
|
||||
/* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */
|
||||
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
|
||||
/* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */
|
||||
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM)
|
||||
/* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
/* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
#endif
|
||||
|
||||
/* Ensure UART pins are in native mode for H1. */
|
||||
/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
|
||||
/* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
|
||||
|
||||
/* C23 : UART2_CTS# ==> PCH_WP */
|
||||
PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
|
||||
|
||||
/* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
|
||||
PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
|
||||
CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
|
||||
};
|
||||
|
||||
const struct cros_gpio *variant_cros_gpios(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(cros_gpios);
|
||||
return cros_gpios;
|
||||
}
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2017 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/acpi/dptf.asl>
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2017 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __MAINBOARD_EC_H__
|
||||
#define __MAINBOARD_EC_H__
|
||||
|
||||
#include <ec/ec.h>
|
||||
#include <ec/google/chromeec/ec_commands.h>
|
||||
|
||||
#include <variant/gpio.h>
|
||||
|
||||
#define MAINBOARD_EC_SCI_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
|
||||
|
||||
#define MAINBOARD_EC_SMI_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
|
||||
|
||||
/* EC can wake from S5 with lid or power button */
|
||||
#define MAINBOARD_EC_S5_WAKE_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
|
||||
|
||||
/*
|
||||
* EC can wake from S3 with lid or power button or key press or
|
||||
* mode change event.
|
||||
*/
|
||||
#define MAINBOARD_EC_S3_WAKE_EVENTS \
|
||||
(MAINBOARD_EC_S5_WAKE_EVENTS |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
|
||||
|
||||
/* Log EC wake events plus EC shutdown events */
|
||||
#define MAINBOARD_EC_LOG_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
|
||||
|
||||
/*
|
||||
* ACPI related definitions for ASL code.
|
||||
*/
|
||||
|
||||
/* Enable EC backed ALS device in ACPI */
|
||||
#define EC_ENABLE_ALS_DEVICE
|
||||
|
||||
/* Enable EC backed PD MCU device in ACPI */
|
||||
#define EC_ENABLE_PD_MCU_DEVICE
|
||||
|
||||
/* Enable LID switch and provide wake pin for EC */
|
||||
#define EC_ENABLE_LID_SWITCH
|
||||
#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
|
||||
#define EC_ENABLE_TABLET_EVENT
|
||||
|
||||
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
|
||||
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
|
||||
#define SIO_EC_ENABLE_P2SK
|
||||
|
||||
#endif /* __MAINBOARD_EC_H__ */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2017 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __MAINBOARD_GPIO_H__
|
||||
#define __MAINBOARD_GPIO_H__
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
#endif /* __MAINBOARD_GPIO_H__ */
|
||||
Loading…
Reference in New Issue