diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md
index 40589a1234..4f2b00e153 100644
--- a/Documentation/releases/coreboot-4.14-relnotes.md
+++ b/Documentation/releases/coreboot-4.14-relnotes.md
@@ -142,7 +142,7 @@ primarily to serve the needs of the server market.
 
 coreboot support for Xeon-SP is in src/soc/intel/xeon_sp directory.
 This release has support for SkyLake-SP (SKX-SP) which is the 2nd
-generation, and for CooperLake-SP (CPX-SP) which is the 3rd generation
+generation, and for Cooper Lake-SP (CPX-SP) which is the 3rd generation
 or the latest generation [2] on market.
 
 With this release, the codebase for multiple generations of Xeon-SP
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index d912f1776f..0f025ac99e 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -20,7 +20,7 @@ config SOC_INTEL_COOPERLAKE_SP
 	select PLATFORM_USES_FSP2_2
 	select CACHE_MRC_SETTINGS
 	help
-	  Intel Cooperlake-SP support
+	  Intel Cooper Lake-SP support
 
 if XEON_SP_COMMON_BASE
 
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 19bf2af7e5..a4da3443c0 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -186,7 +186,7 @@ static void chip_init(void *data)
 }
 
 struct chip_operations soc_intel_xeon_sp_cpx_ops = {
-	CHIP_NAME("Intel Cooperlake-SP")
+	CHIP_NAME("Intel Cooper Lake-SP")
 	.enable_dev = chip_enable_dev,
 	.init = chip_init,
 	.final = chip_final,