From 555c3b1d9b05033be0e49ec62fba43536efd410f Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 19 Aug 2020 21:44:36 +0200 Subject: [PATCH] soc/nvidia: Drop unneeded empty lines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I76430f5cd4b661aff85e2d21722f41c03362b1bd Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/44598 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/nvidia/tegra/dc.h | 1 - src/soc/nvidia/tegra/displayport.h | 1 - src/soc/nvidia/tegra/usb.h | 1 - src/soc/nvidia/tegra124/dp.c | 1 - .../nvidia/tegra124/lp0/tegra_lp0_resume.c | 42 ------------------- src/soc/nvidia/tegra124/sdram.c | 1 - src/soc/nvidia/tegra124/spi.c | 3 -- src/soc/nvidia/tegra124/uart.c | 1 - src/soc/nvidia/tegra210/bootblock.c | 1 - src/soc/nvidia/tegra210/dc.c | 1 - src/soc/nvidia/tegra210/dp.c | 2 - src/soc/nvidia/tegra210/dsi.c | 3 -- src/soc/nvidia/tegra210/include/soc/ccplex.h | 1 - src/soc/nvidia/tegra210/include/soc/id.h | 1 - .../nvidia/tegra210/include/soc/mipi-phy.h | 1 - .../nvidia/tegra210/lp0/tegra_lp0_resume.c | 11 ----- src/soc/nvidia/tegra210/spi.c | 3 -- src/soc/nvidia/tegra210/uart.c | 1 - 18 files changed, 76 deletions(-) diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index 27bbee80e6..6743a105c4 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -348,7 +348,6 @@ struct display_controller { }; check_member(display_controller, winbuf, 0x800 * 4); - /* DC_CMD_DISPLAY_COMMAND 0x032 */ #define DISP_COMMAND_RAISE (1 << 0) #define DISP_CTRL_MODE_STOP (0 << 5) diff --git a/src/soc/nvidia/tegra/displayport.h b/src/soc/nvidia/tegra/displayport.h index 0828755272..0e3e2fe4f0 100644 --- a/src/soc/nvidia/tegra/displayport.h +++ b/src/soc/nvidia/tegra/displayport.h @@ -326,7 +326,6 @@ struct tegra_dc_dp_data { int enabled; }; - /* DPCD definitions */ /* you know, all the vendors pick their own set of defines. * All of them. diff --git a/src/soc/nvidia/tegra/usb.h b/src/soc/nvidia/tegra/usb.h index 387fb676ea..c6336e54e2 100644 --- a/src/soc/nvidia/tegra/usb.h +++ b/src/soc/nvidia/tegra/usb.h @@ -3,7 +3,6 @@ #ifndef __SOC_NVIDIA_TEGRA_USB_H__ #define __SOC_NVIDIA_TEGRA_USB_H__ - enum usb_phy_type { /* For use in lpm_ctrl[31:29] */ USB_PHY_UTMIP = 0, USB_PHY_ULPI = 2, diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index e3885bf834..4155c34b21 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -616,7 +616,6 @@ static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp, if (link_cfg->hblank_sym < 0) link_cfg->hblank_sym = 0; - /* Refer to dev_disp.ref for more information. */ /* # symbols/vblank = ((SetRasterBlankStart.X - */ /* SetRasterBlankEen.X - 25) * link_clk / pclk) */ diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index b7881de6a1..38a385cd29 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -12,21 +12,15 @@ enum { SYSCTR_CTLR_BASE = 0x700f0000 }; - - /* UP tag registers. */ static uint32_t *up_tag_ptr = (void *)(UP_TAG_BASE + 0x0); enum { UP_TAG_AVP = 0xaaaaaaaa }; - - /* Timer registers. */ static uint32_t *timer_us_ptr = (void *)(TIMER_BASE + 0x10); - - /* Clock and reset controller registers. */ static uint32_t *clk_rst_rst_devices_l_ptr = (void *)(CLK_RST_BASE + 0x4); enum { @@ -152,14 +146,9 @@ enum { CLR_NONCPURESET = 0x1 << 29 }; - - /* Reset vector. */ - static uint32_t *evp_cpu_reset_ptr = (void *)(TEGRA_EVP_BASE + 0x100); - - /* Flow controller registers. */ static uint32_t *flow_ctlr_halt_cop_events_ptr = (void *)(FLOW_CTLR_BASE + 0x4); @@ -185,7 +174,6 @@ enum { RAM_REPAIR_STS = 0x1 << 1, }; - /* Power management controller registers. */ enum { PARTID_CRAIL = 0, @@ -220,8 +208,6 @@ enum { PMC_XOFS_MASK = 0x3f << PMC_XOFS_SHIFT }; - - /* Memory controller registers. */ static uint32_t *mc_video_protect_size_mb_ptr = (void *)(MC_CTLR_BASE + 0x64c); @@ -232,8 +218,6 @@ enum { VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS = 0x1 << 1 }; - - /* System counter registers. */ static uint32_t *sysctr_cntcr_ptr = (void *)(SYSCTR_CTLR_BASE + 0x0); enum { @@ -243,10 +227,7 @@ enum { static uint32_t *sysctr_cntfid0_ptr = (void *)(SYSCTR_CTLR_BASE + 0x20); - - /* Utility functions. */ - static __always_inline void __noreturn halt(void) { for (;;); @@ -285,10 +266,7 @@ static void udelay(unsigned int usecs) ; } - - /* Accessors. */ - static int wakeup_on_lp(void) { return !!(read32(pmc_ctlr_scratch4_ptr) & PMC_SCRATCH4_LP); @@ -304,10 +282,7 @@ static unsigned int get_osc_freq(void) return (read32(clk_rst_osc_ctrl_ptr) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; } - - /* Clock configuration. */ - static void config_oscillator(void) { // Read oscillator drive strength from OSC_EDPD_OVER.XOFS and copy @@ -416,10 +391,7 @@ static void enable_cpu_clocks(void) write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_CPUG | CLK_ENB_CPULP); } - - /* Function unit configuration. */ - static void config_core_sight(void) { // Enable the CoreSight clock. @@ -449,10 +421,7 @@ static void config_mselect(void) write32(clk_rst_rst_dev_v_clr_ptr, SWR_MSELECT_RST); } - - /* Resets. */ - static void clear_cpu_resets(void) { // Take the non-cpu of the G and LP clusters out of reset. @@ -471,10 +440,7 @@ static void clear_cpu_resets(void) CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3); } - - /* RAM repair */ - void ram_repair(void) { // Request Cluster0 RAM repair. @@ -490,9 +456,7 @@ void ram_repair(void) ; } - /* Power. */ - static void power_on_partition(unsigned int id) { uint32_t bit = 0x1 << id; @@ -544,10 +508,7 @@ static void power_on_main_cpu(void) write32(pmc_ctlr_cpupwrgood_timer_ptr, orig_timer); } - - /* Entry point. */ - void lp0_resume(void) { // If not on the AVP, reset. @@ -608,10 +569,7 @@ void lp0_resume(void) FLOW_MODE_STOP | EVENT_JTAG); } - - /* Header. */ - extern uint8_t blob_data; extern uint8_t blob_data_size; extern uint8_t blob_total_size; diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c index 30ceee6006..01444a1d02 100644 --- a/src/soc/nvidia/tegra124/sdram.c +++ b/src/soc/nvidia/tegra124/sdram.c @@ -11,7 +11,6 @@ #include #include - static void sdram_patch(uintptr_t addr, uint32_t value) { if (addr) diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 18ea626d57..3a078f8573 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -335,7 +335,6 @@ static void tegra_spi_wait(struct tegra_spi_channel *spi) spi_delay(spi, dma_blk - count); } - static int fifo_error(struct tegra_spi_channel *spi) { return read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR ? 1 : 0; @@ -523,8 +522,6 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi) setbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); if (spi->dma_in) dma_start(spi->dma_in); - - } static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index 4f24c0da66..aba8dd954d 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -5,7 +5,6 @@ #include #include - struct tegra124_uart { union { uint32_t thr; // Transmit holding register. diff --git a/src/soc/nvidia/tegra210/bootblock.c b/src/soc/nvidia/tegra210/bootblock.c index ce5eaf20ca..1657d7ce44 100644 --- a/src/soc/nvidia/tegra210/bootblock.c +++ b/src/soc/nvidia/tegra210/bootblock.c @@ -179,7 +179,6 @@ void tegra210_main(void) pmc_print_rst_status(); - bootblock_mainboard_init(); printk(BIOS_INFO, "T210 bootblock: Mainboard bootblock init done\n"); diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c index 7da5d2117d..8625f76a8c 100644 --- a/src/soc/nvidia/tegra210/dc.c +++ b/src/soc/nvidia/tegra210/dc.c @@ -91,7 +91,6 @@ int update_display_mode(struct display_controller *disp_ctrl, WRITEL(config->vsync_width << 16 | config->hsync_width, &disp_ctrl->disp.sync_width); - WRITEL((config->vback_porch << 16) | config->hback_porch, &disp_ctrl->disp.back_porch); diff --git a/src/soc/nvidia/tegra210/dp.c b/src/soc/nvidia/tegra210/dp.c index 82923c3cfe..9c55242765 100644 --- a/src/soc/nvidia/tegra210/dp.c +++ b/src/soc/nvidia/tegra210/dp.c @@ -631,7 +631,6 @@ static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp, if (link_cfg->hblank_sym < 0) link_cfg->hblank_sym = 0; - /* Refer to dev_disp.ref for more information. */ /* # symbols/vblank = ((SetRasterBlankStart.X - */ /* SetRasterBlankEen.X - 25) * link_clk / pclk) */ @@ -1189,7 +1188,6 @@ static int tegra_dc_dp_fast_link_training(struct tegra_dc_dp_data *dp, int j; u32 mask = 0xffff >> ((4 - link_cfg->lane_count) * 4); - printk(BIOS_INFO, "dp: %s\n", __func__); tegra_dc_sor_set_lane_parm(sor, link_cfg); diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c index 3ee114e177..5026ef4b58 100644 --- a/src/soc/nvidia/tegra210/dsi.c +++ b/src/soc/nvidia/tegra210/dsi.c @@ -434,7 +434,6 @@ static int tegra_output_dsi_enable(struct tegra_dsi *dsi, return 0; } - static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, unsigned int vrefresh) { @@ -520,8 +519,6 @@ static int tegra_output_dsi_setup_clock(struct tegra_dsi *dsi, return plld/1000000; } - - static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) { unsigned long value; diff --git a/src/soc/nvidia/tegra210/include/soc/ccplex.h b/src/soc/nvidia/tegra210/include/soc/ccplex.h index 3975f44445..b27d5abc16 100644 --- a/src/soc/nvidia/tegra210/include/soc/ccplex.h +++ b/src/soc/nvidia/tegra210/include/soc/ccplex.h @@ -3,7 +3,6 @@ #ifndef __SOC_NVIDIA_TEGRA210_CCPLEX_H__ #define __SOC_NVIDIA_TEGRA210_CCPLEX_H__ - #define MTS_LOAD_ADDRESS 0x82000000 /* Prepare the clocks and rails to start the cpu. */ diff --git a/src/soc/nvidia/tegra210/include/soc/id.h b/src/soc/nvidia/tegra210/include/soc/id.h index 5c5097ab66..56c3355fe6 100644 --- a/src/soc/nvidia/tegra210/include/soc/id.h +++ b/src/soc/nvidia/tegra210/include/soc/id.h @@ -3,7 +3,6 @@ #ifndef __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ID_H__ #define __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ID_H__ - #include #include diff --git a/src/soc/nvidia/tegra210/include/soc/mipi-phy.h b/src/soc/nvidia/tegra210/include/soc/mipi-phy.h index 4a53a07853..ec5c54ea3b 100644 --- a/src/soc/nvidia/tegra210/include/soc/mipi-phy.h +++ b/src/soc/nvidia/tegra210/include/soc/mipi-phy.h @@ -2,7 +2,6 @@ #ifndef _TEGRA_MIPI_PHY_H #define _TEGRA_MIPI_PHY_H - /* * Macros for calculating the phy timings */ diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index 0740d36807..9e2754d05f 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -26,7 +26,6 @@ enum { UP_TAG_AVP = 0xaaaaaaaa }; - /* APB Misc JTAG Configuration Register */ static uint32_t *misc_pp_config_ctl_ptr = (void *)(APB_MISC_BASE + 0x24); enum { @@ -40,7 +39,6 @@ enum { CFG2TMC_RAM_SVOP_PDP_VAL_2 = 0x2 << 24, }; - /* PINMUX registers. */ static uint32_t *pinmux_pwr_i2c_scl_ptr = (void *)(PINMUX_BASE + 0xdc); static uint32_t *pinmux_pwr_i2c_sda_ptr = (void *)(PINMUX_BASE + 0xe0); @@ -57,7 +55,6 @@ enum { static uint32_t *timer_us_ptr = (void *)(TIMER_BASE + 0x10); static uint32_t *timer_us_cfg_ptr = (void *)(TIMER_BASE + 0x14); - /* Clock and reset controller registers. */ static uint32_t *clk_rst_rst_devices_l_ptr = (void *)(CLK_RST_BASE + 0x4); enum { @@ -264,7 +261,6 @@ enum { ACTIVE_SLOW = 0x1 << 0 }; - /* Power management controller registers. */ enum { PARTID_CRAIL = 0, @@ -346,7 +342,6 @@ enum { static uint32_t *sb_aa64_reset_low = (void *)(SECURE_BOOT_BASE + 0x30); static uint32_t *sb_aa64_reset_high = (void *)(SECURE_BOOT_BASE + 0x34); - /* EMC registers */ static uint32_t *pmacro_cfg_pm_global = (void *)(EMC_BASE + 0xc30); enum { @@ -408,7 +403,6 @@ enum { #define MAX77621_VOUT_VAL (0x80 | 0x27) #define MAX77621_VOUT_DATA (MAX77621_VOUT_REG | (MAX77621_VOUT_VAL << 8)) - /* Utility functions. */ static __always_inline void __noreturn halt(void) @@ -592,7 +586,6 @@ static void enable_select_cpu_clocks(void) udelay(10); } - /* Function unit configuration. */ static void config_core_sight(void) @@ -609,7 +602,6 @@ static void config_core_sight(void) write32(clk_rst_rst_dev_u_clr_ptr, SWR_CSITE_RST); } - /* RAM repair */ void ram_repair(void) @@ -621,7 +613,6 @@ void ram_repair(void) ; } - /* Power. */ static void power_on_partition(unsigned int id) @@ -764,7 +755,6 @@ static void mbist_workaround(void) write32(clk_rst_lvl2_clk_gate_ovrd_ptr, 0x01000000); /* QSPI OVR=1 */ write32(clk_rst_lvl2_clk_gate_ovre_ptr, 0x00000c00); - clks_to_be_cleared = read32(clk_rst_clk_out_enb_l_ptr); clks_to_be_cleared &= ~MBIST_CLK_ENB_L_0; write32(clk_rst_clk_enb_l_clr_ptr, clks_to_be_cleared); @@ -1085,7 +1075,6 @@ void lp0_resume(void) FLOW_MODE_STOP | EVENT_JTAG); } - /* Header. */ extern uint8_t blob_data; diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index 067d77e51e..66f9fd8c93 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -319,7 +319,6 @@ static void tegra_spi_wait(struct tegra_spi_channel *spi) ASSERT(spi_byte_count(spi) == dma_blk_count); } - static int fifo_error(struct tegra_spi_channel *spi) { return read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR ? 1 : 0; @@ -550,8 +549,6 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi) setbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); if (spi->dma_in) dma_start(spi->dma_in); - - } static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c index 7dbaf7b207..98c3d4ca9c 100644 --- a/src/soc/nvidia/tegra210/uart.c +++ b/src/soc/nvidia/tegra210/uart.c @@ -26,7 +26,6 @@ struct tegra210_uart { uint32_t msr; // Modem status register. } __packed; - static struct tegra210_uart * const uart_ptr = (void *)CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS;