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google/stout: Implement functions required by CHROMEOS 

BRANCH=none
BUG=chromium:513990
TEST=google/stout builds

Change-Id: I00de7524297e4471a9f7d6afd0d2b991d29020e9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b85c54af7d4def45f014ee1d9b79df0b649f90f7
Original-Change-Id: I0870dd11c97cecc932a135f73be8234a88c0622b
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288860
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/11064
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Patrick Georgi 2015-07-27 23:18:15 +02:00 committed by Patrick Georgi
parent c3f72751f8
commit 556538af85
1 changed files with 26 additions and 10 deletions
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36
src/mainboard/google/stout/chromeos.c
View File

@ -35,21 +35,13 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
if (!gpio_base)
return;
u32 gp_lvl = inl(gpio_base + GP_LVL);
gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
gpios->count = GPIO_COUNT;
/* Write Protect: GPIO7 */
gpios->gpios[0].port = 7;
gpios->gpios[0].polarity = ACTIVE_LOW;
gpios->gpios[0].value = (gp_lvl >> 7) & 1;
gpios->gpios[0].value = !get_write_protect_state();
strncpy((char *)gpios->gpios[0].name,"write protect",
GPIO_MAX_NAME_LENGTH);
@ -68,7 +60,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
/* Lid Switch: Virtual switch */
gpios->gpios[3].port = -1;
gpios->gpios[3].polarity = ACTIVE_HIGH;
gpios->gpios[3].value = 1; /* Hard-code to open */
gpios->gpios[3].value = get_lid_switch();
strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
/* Power Button: Virtual switch */
@ -91,6 +83,30 @@ void fill_lb_gpios(struct lb_gpios *gpios)
}
#endif
int get_write_protect_state(void)
{
device_t dev;
#ifdef __PRE_RAM__
dev = PCI_DEV(0, 0x1f, 0);
#else
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
#endif
u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
if (!gpio_base)
return 0;
u32 gp_lvl = inl(gpio_base + GP_LVL);
return !((gp_lvl >> 7) & 1);
}
int get_lid_switch(void)
{
/* hard-code to open */
return 1;
}
/* The dev-switch is virtual on Stout (and so handled elsewhere). */
int get_developer_mode_switch(void)
{