From 55812d6430b3bcab3961943621fe2784a3e2b79a Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 16 Jan 2023 13:24:47 +0530 Subject: [PATCH] soc/intel/alderlake: Avoid redundant chipset programming in romstage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch refactors the mainboard_romstage_entry() function to avoid redundant chipset programming caused by global reset due to CSE FW sync operation. Hence, keeping only the minimal and mandatory operations required to perform CSE FW sync successfully. This would help to optimize the boot flow by removing redundant programming like SA, SMBUS twice in every CSE FW update path. TEST=Able to build and boot Google/Marasov successfully. Signed-off-by: Subrata Banik Change-Id: Iba9767ef51d7fc7ecf9de14454105865433ba041 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71932 Reviewed-by: Sridhar Siricilla Reviewed-by: Sean Rhodes Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/romstage/romstage.c | 28 ++++++++++----------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 52c77be325..2927d12e5a 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -128,15 +128,26 @@ static void save_dimm_info(void) void mainboard_romstage_entry(void) { - bool s3wake; struct chipset_power_state *ps = pmc_get_power_state(); + bool s3wake = pmc_fill_power_state(ps) == ACPI_S3; + + /* Initialize HECI interface */ + cse_init(HECI1_BASE_ADDRESS); + + if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE)) + dbg_feature_cntrl_init(); + + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) { + timestamp_add_now(TS_CSE_FW_SYNC_START); + cse_fw_sync(); + timestamp_add_now(TS_CSE_FW_SYNC_END); + } /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program SMBus base address and enable it */ smbus_common_init(); - /* Initialize HECI interface */ - cse_init(HECI1_BASE_ADDRESS); + /* * Disable Intel TXT if `CPU is unsupported` or `SoC haven't selected the config`. * @@ -145,17 +156,6 @@ void mainboard_romstage_entry(void) if (!CONFIG(INTEL_TXT)) disable_intel_txt(); - if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE)) - dbg_feature_cntrl_init(); - - s3wake = pmc_fill_power_state(ps) == ACPI_S3; - - if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) { - timestamp_add_now(TS_CSE_FW_SYNC_START); - cse_fw_sync(); - timestamp_add_now(TS_CSE_FW_SYNC_END); - } - /* Update coreboot timestamp table with CSE timestamps */ if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY)) cse_get_telemetry_data();