mb/google/sarien: Add new mainboard
Sarien is a new board using Intel Whiskey Lake SOC. It also uses the newly added Wilco EC, enabled in a separate commit. Sarien is not a true reference board, it is just one variant of a very similar design. For that reason it is not considered the baseboard but rather a standalone variant. Change-Id: I2e38f617694ed2c2ef746ff8083f2bfd58cbc775 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Duncan Laurie
Duncan Laurie
parent
db48f7ea48
commit
558602ff40
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@ -0,0 +1,89 @@
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config BOARD_GOOGLE_BASEBOARD_SARIEN
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def_bool n
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select DRIVERS_SPI_ACPI
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select DRIVERS_PS2_KEYBOARD
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select GENERIC_SPD_BIN
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_I2C_TPM_CR50
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select MAINBOARD_HAS_TPM2
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select SOC_INTEL_COFFEELAKE
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select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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select TPM2
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if BOARD_GOOGLE_BASEBOARD_SARIEN
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config CHROMEOS
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bool
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default y
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
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select GBB_FLAG_FORCE_MANUAL_RECOVERY
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config DEVICETREE
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string
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default "variants/sarien/devicetree.cb" if BOARD_GOOGLE_SARIEN
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config DIMM_MAX
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int
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default 2
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config DIMM_SPD_SIZE
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int
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default 512
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config DRIVER_TPM_I2C_BUS
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hex
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default 0x4
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config DRIVER_TPM_I2C_ADDR
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hex
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default 0x50
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config TPM_TIS_ACPI_INTERRUPT
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int
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default 82 # GPE0_DW2_18 (GPP_D18)
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config GBB_HWID
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string
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depends on CHROMEOS
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default "SARIEN TEST 2787" if BOARD_GOOGLE_SARIEN
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config MAINBOARD_DIR
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string
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default "google/sarien"
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config MAINBOARD_FAMILY
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string
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default "Google_Sarien" if BOARD_GOOGLE_SARIEN
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config MAINBOARD_PART_NUMBER
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string
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default "Sarien" if BOARD_GOOGLE_SARIEN
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config MAINBOARD_VENDOR
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string
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default "Google"
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config MAX_CPUS
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int
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default 8
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config VARIANT_DIR
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string
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default "sarien" if BOARD_GOOGLE_SARIEN
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config VBOOT
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select HAS_RECOVERY_MRC_CACHE
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select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
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select VBOOT_LID_SWITCH
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endif # BOARD_GOOGLE_BASEBOARD_SARIEN
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@ -0,0 +1,5 @@
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comment "Sarien"
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config BOARD_GOOGLE_SARIEN
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bool "-> Sarien"
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select BOARD_GOOGLE_BASEBOARD_SARIEN
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@ -0,0 +1,28 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright 2018 Google LLC
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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bootblock-y += bootblock.c
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ramstage-y += ramstage.c
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romstage-y += romstage.c
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bootblock-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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subdirs-y += variants/$(VARIANT_DIR)
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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@ -0,0 +1,6 @@
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Vendor name: Google
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Board name: Sarien
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Category: laptop
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -0,0 +1,32 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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static void early_config_gpio(void)
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{
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const struct pad_config *early_gpio_table;
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size_t num_gpios = 0;
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early_gpio_table = variant_early_gpio_table(&num_gpios);
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gpio_configure_pads(early_gpio_table, num_gpios);
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}
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void bootblock_mainboard_init(void)
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{
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early_config_gpio();
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}
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@ -0,0 +1,80 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <boot/coreboot_tables.h>
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#include <gpio.h>
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#include <rules.h>
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
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{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
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{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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{-1, ACTIVE_HIGH, 0, "EC in RW"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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static int cros_get_gpio_value(int type)
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{
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const struct cros_gpio *cros_gpios;
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size_t i, num_gpios = 0;
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cros_gpios = variant_cros_gpios(&num_gpios);
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for (i = 0; i < num_gpios; i++) {
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const struct cros_gpio *gpio = &cros_gpios[i];
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if (gpio->type == type) {
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int state = gpio_get(gpio->gpio_num);
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if (gpio->polarity == CROS_GPIO_ACTIVE_LOW)
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return !state;
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else
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return state;
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}
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}
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return 0;
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}
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void mainboard_chromeos_acpi_generate(void)
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{
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const struct cros_gpio *cros_gpios;
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size_t num_gpios = 0;
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cros_gpios = variant_cros_gpios(&num_gpios);
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chromeos_acpi_gpio_generate(cros_gpios, num_gpios);
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}
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int get_write_protect_state(void)
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{
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return cros_get_gpio_value(CROS_GPIO_WP);
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}
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int get_recovery_mode_switch(void)
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{
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return cros_get_gpio_value(CROS_GPIO_REC);
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}
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int get_lid_switch(void)
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{
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return 1;
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}
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@ -0,0 +1,46 @@
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FLASH@0xfe000000 0x2000000 {
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SI_ALL@0x0 0x1000000 {
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SI_DESC@0x0 0x1000
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SI_EC@0x1000 0x100000
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SI_GBE@0x101000 0x2000
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SI_ME@0x103000 0xefd000
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}
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SI_BIOS@0x1000000 0x1000000 {
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RW_SECTION_A@0x0 0x280000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x26ffc0
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RW_FWID_A@0x27ffc0 0x40
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}
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RW_SECTION_B@0x280000 0x280000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x26ffc0
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RW_FWID_B@0x27ffc0 0x40
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}
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RW_MISC@0x500000 0x30000 {
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UNIFIED_MRC_CACHE@0x0 0x20000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x10000
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}
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RW_ELOG@0x20000 0x4000
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RW_SHARED@0x24000 0x4000 {
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SHARED_DATA@0x0 0x2000
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VBLOCK_DEV@0x2000 0x2000
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}
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RW_VPD@0x28000 0x2000
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RW_NVRAM@0x2a000 0x6000
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}
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CONSOLE@0x530000 0x20000
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RW_LEGACY(CBFS)@0x550000 0x6b0000
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WP_RO@0xc00000 0x400000 {
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RO_VPD@0x0 0x4000
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RO_UNUSED@0x4000 0xc000
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RO_SECTION@0x10000 0x3f0000 {
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FMAP@0x0 0x800
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RO_FRID@0x800 0x40
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RO_FRID_PAD@0x840 0x7c0
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GBB@0x1000 0xef000
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COREBOOT(CBFS)@0xf0000 0x300000
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}
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}
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}
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}
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@ -0,0 +1,53 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x05, /* DSDT revision: ACPI v5.0 */
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"COREv4", /* OEM id */
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"COREBOOT", /* OEM table id */
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0x20110725 /* OEM revision */
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)
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{
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/* Some generic macros */
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#include <soc/intel/cannonlake/acpi/platform.asl>
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/* global NVS and variables */
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#include <soc/intel/cannonlake/acpi/globalnvs.asl>
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/* CPU */
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#include <soc/intel/cannonlake/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PWRB)
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{
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Name (_HID, EisaId ("PNP0C0C"))
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}
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Device (PCI0)
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{
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#include <soc/intel/cannonlake/acpi/northbridge.asl>
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#include <soc/intel/cannonlake/acpi/southbridge.asl>
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}
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}
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#if IS_ENABLED(CONFIG_CHROMEOS)
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/* Chrome OS specific */
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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#endif
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/* Chipset specific sleep states */
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#include <soc/intel/cannonlake/acpi/sleepstates.asl>
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}
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@ -0,0 +1,37 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
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#include <arch/acpi.h>
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#include <soc/ramstage.h>
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#include <variant/gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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|
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void mainboard_silicon_init_params(FSP_S_CONFIG *params)
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{
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const struct pad_config *gpio_table;
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size_t num_gpios;
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gpio_table = variant_gpio_table(&num_gpios);
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gpio_configure_pads(gpio_table, num_gpios);
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}
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static void mainboard_enable(struct device *dev)
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{
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dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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@ -0,0 +1,50 @@
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/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Google LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <soc/cnl_memcfg_init.h>
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#include <soc/romstage.h>
|
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|
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static const struct cnl_mb_cfg memcfg = {
|
||||
/*
|
||||
* The dqs_map arrays map the ddr4 pins to the SoC pins
|
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* for both channels.
|
||||
*
|
||||
* the index = pin number on ddr4 part
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* the value = pin number on SoC
|
||||
*/
|
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.dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 },
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.dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 },
|
||||
|
||||
/* Baseboard uses 121, 81 and 100 rcomp resistors */
|
||||
.rcomp_resistor = { 121, 81, 100 },
|
||||
|
||||
/*
|
||||
* Baseboard Rcomp target values.
|
||||
*/
|
||||
.rcomp_targets = { 100, 40, 20, 20, 26 },
|
||||
|
||||
/* Disable Early Command Training */
|
||||
.ect = 0,
|
||||
};
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
|
||||
{
|
||||
const struct spd_info spd = {
|
||||
.spd_smbus_address[0] = 0xa0,
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||||
.spd_smbus_address[2] = 0xa4
|
||||
};
|
||||
|
||||
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg, &spd);
|
||||
}
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright 2018 Google LLC
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
bootblock-y += gpio.c
|
||||
ramstage-y += gpio.c
|
||||
romstage-y += gpio.c
|
||||
verstage-y += gpio.c
|
||||
|
|
@ -0,0 +1,163 @@
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chip soc/intel/cannonlake
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
# route. i.e. If this route changes then the affected GPE
|
||||
# offset bits also need to be changed.
|
||||
register "gpe0_dw0" = "PMC_GPP_A"
|
||||
register "gpe0_dw1" = "PMC_GPP_C"
|
||||
register "gpe0_dw2" = "PMC_GPP_D"
|
||||
|
||||
# FSP configuration
|
||||
register "SaGv" = "3"
|
||||
register "HeciEnabled" = "1"
|
||||
register "SataSalpSupport" = "1"
|
||||
register "SataMode" = "0"
|
||||
register "SataPortsEnable[0]" = "1"
|
||||
register "SataPortsEnable[1]" = "1"
|
||||
register "SataPortsEnable[2]" = "1"
|
||||
register "SataPortsDevSlp[0]" = "1"
|
||||
register "SataPortsDevSlp[1]" = "1"
|
||||
register "SataPortsDevSlp[2]" = "1"
|
||||
register "InternalGfx" = "1"
|
||||
register "SkipExtGfxScan" = "1"
|
||||
register "VmxEnable" = "1"
|
||||
|
||||
register "speed_shift_enable" = "1"
|
||||
register "s0ix_enable" = "1"
|
||||
|
||||
# Intel Common SoC Config
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
|
||||
register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Ext USB2 Port 1 Charge
|
||||
register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Ext USB2 Port 2
|
||||
register "usb2_ports[3]" = "USB2_PORT_LONG(OC2)" # Ext USB2 Port 3
|
||||
register "usb2_ports[4]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH
|
||||
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # FPR in PB
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 2230 (BT)
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Ext USB3 Port 1 Charge
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Ext USB3 Port 2
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Ext USB3 Port 3
|
||||
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 3042 (WWAN)
|
||||
register "usb3_ports[5]" = "USB3_PORT_EMPTY"
|
||||
|
||||
# Intel Common SoC Config
|
||||
#+-------------------+---------------------------+
|
||||
#| Field | Value |
|
||||
#+-------------------+---------------------------+
|
||||
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
|
||||
#| I2C0 | Touchscreen |
|
||||
#| I2C1 | Touchpad |
|
||||
#| I2C4 | H1 TPM |
|
||||
#+-------------------+---------------------------+
|
||||
register "common_soc_config" = "{
|
||||
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
|
||||
.i2c[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
.i2c[1] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
.i2c[4] = {
|
||||
.early_init = 1,
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
}"
|
||||
|
||||
# PCIe port 8 for Card Reader
|
||||
register "PcieRpEnable[7]" = "1"
|
||||
register "PcieClkSrcUsage[4]" = "7"
|
||||
register "PcieClkSrcClkReq[4]" = "4"
|
||||
|
||||
# PCIe port 9 for LAN
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieClkSrcUsage[3]" = "8"
|
||||
register "PcieClkSrcClkReq[3]" = "3"
|
||||
|
||||
# PCIe port 10 for M.2 2230 WLAN
|
||||
register "PcieRpEnable[9]" = "1"
|
||||
register "PcieClkSrcUsage[1]" = "9"
|
||||
register "PcieClkSrcClkReq[1]" = "1"
|
||||
|
||||
# PCIe port 12 for M.2 3042
|
||||
register "PcieRpEnable[11]" = "1"
|
||||
register "PcieClkSrcUsage[0]" = "11"
|
||||
register "PcieClkSrcClkReq[0]" = "0"
|
||||
|
||||
# PCIe port 13 for M.2 2280 SSD
|
||||
register "PcieRpEnable[12]" = "1"
|
||||
register "PcieClkSrcUsage[2]" = "12"
|
||||
register "PcieClkSrcClkReq[2]" = "2"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 04.0 on end # SA Thermal device
|
||||
device pci 12.0 on end # Thermal Subsystem
|
||||
device pci 12.5 off end # UFS SCS
|
||||
device pci 12.6 off end # GSPI #2
|
||||
device pci 14.0 on end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
device pci 14.5 off end # SDCard
|
||||
device pci 15.0 on end # I2C #0
|
||||
device pci 15.1 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ACPI0C50""
|
||||
register "generic.desc" = ""Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
|
||||
register "hid_desc_reg_offset" = "0x20"
|
||||
device i2c 2c on end
|
||||
end
|
||||
end # I2C #1
|
||||
device pci 15.2 off end # I2C #2
|
||||
device pci 15.3 off end # I2C #3
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 16.5 off end # Management Engine Interface 4
|
||||
device pci 17.0 on end # SATA
|
||||
device pci 19.0 on
|
||||
chip drivers/i2c/tpm
|
||||
register "hid" = ""GOOG0005""
|
||||
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)"
|
||||
device i2c 50 on end
|
||||
end
|
||||
end # I2C #4
|
||||
device pci 19.1 off end # I2C #5
|
||||
device pci 19.2 on end # UART #2
|
||||
device pci 1a.0 off end # eMMC
|
||||
device pci 1c.0 on end # PCI Express Port 1 (USB)
|
||||
device pci 1c.1 off end # PCI Express Port 2 (USB)
|
||||
device pci 1c.2 off end # PCI Express Port 3 (USB)
|
||||
device pci 1c.3 off end # PCI Express Port 4 (USB)
|
||||
device pci 1c.4 off end # PCI Express Port 5 (USB)
|
||||
device pci 1c.5 off end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 on end # PCI Express Port 8
|
||||
device pci 1d.0 on end # PCI Express Port 9
|
||||
device pci 1d.1 on end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 on end # PCI Express Port 12
|
||||
device pci 1d.4 on end # PCI Express Port 13 (x4)
|
||||
device pci 1e.0 off end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1f.0 on end # LPC/eSPI
|
||||
device pci 1f.1 on end # P2SB
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 on end # GbE
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,263 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Google LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <variant/gpio.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
|
||||
/* Pad configuration in ramstage */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* RCIN# */ PAD_NC(GPP_A0, NONE),
|
||||
/* ESPI_IO0 */
|
||||
/* ESPI_IO1 */
|
||||
/* ESPI_IO2 */
|
||||
/* ESPI_IO3 */
|
||||
/* ESPI_CS# */
|
||||
/* SERIRQ */
|
||||
/* PIRQA# */ PAD_NC(GPP_A7, NONE),
|
||||
/* CLKRUN# */ PAD_NC(GPP_A8, NONE),
|
||||
/* ESPI_CLK */
|
||||
/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE),
|
||||
/* PME# */ PAD_NC(GPP_A11, NONE),
|
||||
/* BM_BUSY# */ PAD_NC(GPP_A12, NONE),
|
||||
/* SUSWARN# */ PAD_NC(GPP_A13, NONE),
|
||||
/* ESPI_RESET# */
|
||||
/* SUSACK# */ PAD_NC(GPP_A15, NONE),
|
||||
/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE),
|
||||
/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE),
|
||||
/* ISH_GP0 */ PAD_NC(GPP_A18, NONE),
|
||||
/* ISH_GP1 */ PAD_NC(GPP_A19, NONE),
|
||||
/* ISH_GP2 */ PAD_NC(GPP_A20, NONE),
|
||||
/* ISH_GP3 */ PAD_NC(GPP_A21, NONE),
|
||||
/* ISH_GP4 */ PAD_NC(GPP_A22, NONE),
|
||||
/* ISH_GP5 */ PAD_NC(GPP_A23, NONE),
|
||||
|
||||
/* CORE_VID0 */
|
||||
/* CORE_VID1 */
|
||||
/* VRALERT# */ PAD_NC(GPP_B2, NONE),
|
||||
/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP,
|
||||
EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */
|
||||
/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */
|
||||
/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
|
||||
/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
|
||||
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
|
||||
/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
|
||||
/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
|
||||
/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE),
|
||||
/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */
|
||||
/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE),
|
||||
/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE),
|
||||
/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE),
|
||||
/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),
|
||||
/* GSPI1_CS# */ PAD_CFG_GPI_APIC(GPP_B19, NONE, DEEP,
|
||||
EDGE_SINGLE, INVERT), /* HDD_FALL_INT */
|
||||
/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */
|
||||
/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */
|
||||
/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE),
|
||||
/* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K),
|
||||
|
||||
/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */
|
||||
/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */
|
||||
/* SMBALERT# */ PAD_NC(GPP_C2, DN_20K),
|
||||
/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */
|
||||
/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */
|
||||
/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K),
|
||||
/* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */
|
||||
/* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */
|
||||
/* UART0_RXD */ PAD_NC(GPP_C8, NONE),
|
||||
/* UART0_TXD */ PAD_NC(GPP_C9, NONE),
|
||||
/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */
|
||||
/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */
|
||||
/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP,
|
||||
EDGE_SINGLE), /* SIO_EXT_WAKE# */
|
||||
/* UART1_TXD */ PAD_NC(GPP_C13, NONE),
|
||||
/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */
|
||||
/* UART1_CTS# */ PAD_NC(GPP_C15, NONE),
|
||||
/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */
|
||||
/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */
|
||||
/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */
|
||||
/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */
|
||||
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
|
||||
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
|
||||
/* UART2_RTS# */ PAD_NC(GPP_C22, NONE),
|
||||
/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP,
|
||||
EDGE_SINGLE, INVERT), /* TS_INT# */
|
||||
|
||||
/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, DEEP,
|
||||
EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */
|
||||
/* SPI1_CLK */ PAD_NC(GPP_D1, NONE),
|
||||
/* SPI1_MISO */ PAD_NC(GPP_D2, NONE),
|
||||
/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE),
|
||||
/* FASHTRIG */ PAD_NC(GPP_D4, NONE),
|
||||
/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE),
|
||||
/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE),
|
||||
/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE),
|
||||
/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE),
|
||||
/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */
|
||||
/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE),
|
||||
/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */
|
||||
/* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE),
|
||||
/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE),
|
||||
/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE),
|
||||
/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */
|
||||
/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE),
|
||||
/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */
|
||||
/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,
|
||||
EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
|
||||
/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE),
|
||||
/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE),
|
||||
/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */
|
||||
/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* WWAN_GPIO_PERST# */
|
||||
/* I2S_MCLK */ PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP,
|
||||
EDGE_SINGLE), /* WWAN_GPIO_WAKE# */
|
||||
|
||||
/* SATAXPCIE0 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* HDD_DET# */
|
||||
/* M3042_PCIE#_SATA */
|
||||
/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
|
||||
/* M2880_PCIE_SATA# */
|
||||
/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
|
||||
/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
|
||||
/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), /* HDD_DEVSLP */
|
||||
/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */
|
||||
/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */
|
||||
/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */
|
||||
/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */
|
||||
/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */
|
||||
/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */
|
||||
/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_OC2# */
|
||||
/* USB2_OC3# */ PAD_NC(GPP_E12, NONE),
|
||||
/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* HDMI_DP1_HPD */
|
||||
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* CPU_DP2_HPD */
|
||||
/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */
|
||||
/* DDPE_HPD3 */ PAD_CFG_GPI_APIC(GPP_E16, NONE, DEEP,
|
||||
EDGE_SINGLE, INVERT), /* FFS_INT2 */
|
||||
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||
/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
|
||||
/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
|
||||
/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE),
|
||||
/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE),
|
||||
/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE),
|
||||
/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE),
|
||||
|
||||
/* CNV_PA_BLANKING */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */
|
||||
/* GPP_F1 */ PAD_NC(GPP_F1, NONE), /* T406 */
|
||||
/* GPP_F2 */ PAD_NC(GPP_F2, NONE), /* T407 */
|
||||
/* GPP_F3 */ PAD_NC(GPP_F3, NONE),
|
||||
/* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
/* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
|
||||
/* CNV_RGI_DT */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
/* CNV_RGI_RSP */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
|
||||
/* CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* CNV_COEX2 */
|
||||
/* CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */
|
||||
/* GPP_F10 */ PAD_NC(GPP_F10, NONE),
|
||||
/* EMMC_CMD */ PAD_NC(GPP_F11, NONE),
|
||||
/* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE),
|
||||
/* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE),
|
||||
/* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE),
|
||||
/* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE),
|
||||
/* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE),
|
||||
/* EMMC_DATA5 */ PAD_NC(GPP_F17, NONE),
|
||||
/* EMMC_DATA6 */ PAD_NC(GPP_F18, NONE),
|
||||
/* EMMC_DATA7 */ PAD_NC(GPP_F19, NONE),
|
||||
/* EMMC_RCLK */ PAD_NC(GPP_F20, NONE),
|
||||
/* EMMC_CLK */ PAD_NC(GPP_F21, NONE),
|
||||
/* EMMC_RESET# */ PAD_NC(GPP_F22, NONE),
|
||||
/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE),
|
||||
|
||||
/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */
|
||||
/* SD_DATA0 */ PAD_NC(GPP_G1, NONE),
|
||||
/* SD_DATA1 */ PAD_NC(GPP_G2, NONE),
|
||||
/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), /* T383 */
|
||||
/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */
|
||||
/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */
|
||||
/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */
|
||||
/* SD_WP */ PAD_NC(GPP_G7, NONE), /* T384 */
|
||||
|
||||
/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE),
|
||||
/* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */
|
||||
/* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */
|
||||
/* I2S2_RXD */ PAD_NC(GPP_H3, NONE),
|
||||
/* I2C2_SDA */ PAD_NC(GPP_H4, NONE), /* T388 */
|
||||
/* I2C2_SCL */ PAD_NC(GPP_H5, NONE), /* T389 */
|
||||
/* I2C3_SDA */ PAD_NC(GPP_H6, NONE), /* T378 */
|
||||
/* I2C3_SCL */ PAD_NC(GPP_H7, NONE), /* T379 */
|
||||
/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
|
||||
/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
|
||||
/* I2C5_SDA */ PAD_NC(GPP_H10, NONE),
|
||||
/* I2C5_SCL */ PAD_NC(GPP_H11, NONE),
|
||||
/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE),
|
||||
/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE),
|
||||
/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE),
|
||||
/* M2_SKT2_CFG3 */ PAD_NC(GPP_H15, NONE),
|
||||
/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE),
|
||||
/* DPPF_CTRLDATA */ PAD_NC(GPP_H17, NONE),
|
||||
/* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10_GATE# */
|
||||
/* TIMESYNC0 */ PAD_NC(GPP_H19, NONE),
|
||||
/* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE),
|
||||
/* GPP_H21 */ PAD_NC(GPP_H21, NONE),
|
||||
/* GPP_H22 */ PAD_NC(GPP_H22, NONE),
|
||||
/* GPP_H23 */ PAD_NC(GPP_H23, NONE),
|
||||
|
||||
/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */
|
||||
/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */
|
||||
/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */
|
||||
/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */
|
||||
/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */
|
||||
/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */
|
||||
/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */
|
||||
/* GPD7 */ PAD_NC(GPD7, NONE),
|
||||
/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */
|
||||
/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */
|
||||
/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */
|
||||
/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
|
||||
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
|
||||
/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
|
||||
/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
|
||||
/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,
|
||||
EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
|
||||
/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
|
||||
/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */
|
||||
/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AH(GPP_E8, CROS_GPIO_DEVICE_NAME),
|
||||
CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME),
|
||||
};
|
||||
|
||||
const struct cros_gpio *variant_cros_gpios(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(cros_gpios);
|
||||
return cros_gpios;
|
||||
}
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Google LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* Flash Write Protect */
|
||||
#define GPIO_PCH_WP GPP_E15
|
||||
|
||||
/* Recovery mode */
|
||||
#define GPIO_REC_MODE GPP_E8
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num);
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num);
|
||||
|
||||
struct cros_gpio;
|
||||
const struct cros_gpio *variant_cros_gpios(size_t *num);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue