From 55aa17b74410a177db34e7a99e0283c1fbd2903e Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 27 Mar 2015 22:52:18 -0700 Subject: [PATCH] arm64: Correct shareability option for normal memory In order to allow proper working of caches, set the correct shareability option for normal memory. BUG=chrome-os-partner:38222 BRANCH=None TEST=Compiles successfully for foster and SMP works. Change-Id: I5462cb0a2ff94a854f71f58709d7b2e8297ccc44 Signed-off-by: Patrick Georgi Original-Commit-Id: e092916780716ac80c3608c1bd8ca2901fbb3bd1 Original-Change-Id: Idd3c096a004d76a8fd75df2a884fcb97130d0006 Original-Signed-off-by: Furquan Shaikh Original-Reviewed-on: https://chromium-review.googlesource.com/262992 Original-Reviewed-by: Aaron Durbin Original-Tested-by: Furquan Shaikh Original-Trybot-Ready: Furquan Shaikh Original-Commit-Queue: Furquan Shaikh Reviewed-on: http://review.coreboot.org/9898 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/arch/arm64/armv8/mmu.c | 1 + src/arch/arm64/include/armv8/arch/mmu.h | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c index 8fde41f7f7..84b9935a93 100644 --- a/src/arch/arm64/armv8/mmu.c +++ b/src/arch/arm64/armv8/mmu.c @@ -67,6 +67,7 @@ static uint64_t get_block_attr(unsigned long tag) attr |= BLOCK_ACCESS; if (tag & MA_MEM) { + attr |= BLOCK_SH_INNER_SHAREABLE; if (tag & MA_MEM_NC) attr |= BLOCK_INDEX_MEM_NORMAL_NC << BLOCK_INDEX_SHIFT; else diff --git a/src/arch/arm64/include/armv8/arch/mmu.h b/src/arch/arm64/include/armv8/arch/mmu.h index a030b1bf73..564d6afed4 100644 --- a/src/arch/arm64/include/armv8/arch/mmu.h +++ b/src/arch/arm64/include/armv8/arch/mmu.h @@ -65,6 +65,12 @@ #define BLOCK_ACCESS (1 << 10) +#define BLOCK_SH_SHIFT (8) +#define BLOCK_SH_NON_SHAREABLE (0 << BLOCK_SH_SHIFT) +#define BLOCK_SH_UNPREDICTABLE (1 << BLOCK_SH_SHIFT) +#define BLOCK_SH_OUTER_SHAREABLE (2 << BLOCK_SH_SHIFT) +#define BLOCK_SH_INNER_SHAREABLE (3 << BLOCK_SH_SHIFT) + /* XLAT Table Init Attributes */ #define VA_START 0x0