vendorcode/amd/pi/00670F00/Lib: Remove folder
Now that the last dependency was resolved, remove AmdLib folder. BUG=b:112525011 TEST=Build and boot grunt. Change-Id: Ibd9a20bc358742520138b9b01f76d7fd2fac92ab Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28742 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Charles Marslett <charles.marslett@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Richard Spiegel
Patrick Georgi
parent
7717725bfa
commit
55ad8c3af0
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@ -1,573 +0,0 @@
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/* $NoKeywords:$ */
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/**
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* @file
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*
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* AMD Library
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*
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* Contains interface to the AMD AGESA library
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: Lib
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* @e \$Revision: 48409 $ @e \$Date: 2011-03-08 11:19:40 -0600 (Tue, 08 Mar 2011) $
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*
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*/
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/*
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******************************************************************************
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*
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* Copyright (c) 2008 - 2011, Advanced Micro Devices, Inc.
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* 2013 - 2014, Sage Electronic Engineering, LLC
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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||||||
* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************
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*/
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#include <AGESA.h>
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#include <cpuRegisters.h>
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#include "amdlib.h"
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CODE_GROUP (G1_PEICC)
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RDATA_GROUP (G1_PEICC)
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#if !defined(AMDLIB_OPTIMIZE)
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#define AMDLIB_OPTIMIZE
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#endif
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BOOLEAN
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STATIC
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GetPciMmioAddress (
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OUT UINT64 *MmioAddress,
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OUT UINT32 *MmioSize,
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IN AMD_CONFIG_PARAMS *StdHeader
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);
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VOID
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CpuidRead (
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IN UINT32 CpuidFcnAddress,
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OUT CPUID_DATA *Value
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);
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UINT8
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ReadNumberOfCpuCores(
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void
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);
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AMDLIB_OPTIMIZE
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UINT8
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ReadIo8 (
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IN UINT16 Address
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)
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{
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return __inbyte (Address);
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}
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AMDLIB_OPTIMIZE
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UINT16
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ReadIo16 (
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IN UINT16 Address
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)
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{
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return __inword (Address);
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}
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AMDLIB_OPTIMIZE
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UINT32
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ReadIo32 (
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IN UINT16 Address
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)
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{
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return __indword (Address);
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}
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AMDLIB_OPTIMIZE
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VOID
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WriteIo8 (
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IN UINT16 Address,
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IN UINT8 Data
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)
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{
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__outbyte (Address, Data);
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}
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AMDLIB_OPTIMIZE
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VOID
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WriteIo16 (
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IN UINT16 Address,
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IN UINT16 Data
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)
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{
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__outword (Address, Data);
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}
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AMDLIB_OPTIMIZE
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VOID
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WriteIo32 (
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IN UINT16 Address,
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IN UINT32 Data
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)
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{
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__outdword (Address, Data);
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}
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AMDLIB_OPTIMIZE
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STATIC
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UINT64 SetFsBase (
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UINT64 address
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)
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{
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UINT64 hwcr;
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hwcr = __readmsr (0xC0010015);
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__writemsr (0xC0010015, hwcr | 1 << 17);
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__writemsr (0xC0000100, address);
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return hwcr;
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}
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AMDLIB_OPTIMIZE
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STATIC
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VOID
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RestoreHwcr (
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UINT64
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value
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)
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{
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__writemsr (0xC0010015, value);
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}
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AMDLIB_OPTIMIZE
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UINT8
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Read64Mem8 (
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IN UINT64 Address
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)
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{
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UINT8 dataRead;
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UINT64 hwcrSave;
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if ((Address >> 32) == 0) {
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return *(volatile UINT8 *) (UINTN) Address;
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}
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hwcrSave = SetFsBase (Address);
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dataRead = __readfsbyte (0);
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RestoreHwcr (hwcrSave);
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return dataRead;
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}
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AMDLIB_OPTIMIZE
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UINT16
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Read64Mem16 (
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IN UINT64 Address
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)
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{
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UINT16 dataRead;
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UINT64 hwcrSave;
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if ((Address >> 32) == 0) {
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return *(volatile UINT16 *) (UINTN) Address;
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}
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hwcrSave = SetFsBase (Address);
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dataRead = __readfsword (0);
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RestoreHwcr (hwcrSave);
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return dataRead;
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}
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AMDLIB_OPTIMIZE
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UINT32
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Read64Mem32 (
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IN UINT64 Address
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)
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{
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UINT32 dataRead;
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UINT64 hwcrSave;
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if ((Address >> 32) == 0) {
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return *(volatile UINT32 *) (UINTN) Address;
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}
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hwcrSave = SetFsBase (Address);
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dataRead = __readfsdword (0);
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RestoreHwcr (hwcrSave);
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return dataRead;
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}
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AMDLIB_OPTIMIZE
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VOID
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Write64Mem8 (
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IN UINT64 Address,
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IN UINT8 Data
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)
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{
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if ((Address >> 32) == 0){
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*(volatile UINT8 *) (UINTN) Address = Data;
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}
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else {
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UINT64 hwcrSave;
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hwcrSave = SetFsBase (Address);
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__writefsbyte (0, Data);
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RestoreHwcr (hwcrSave);
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}
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}
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AMDLIB_OPTIMIZE
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VOID
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Write64Mem16 (
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IN UINT64 Address,
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IN UINT16 Data
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)
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{
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if ((Address >> 32) == 0){
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*(volatile UINT16 *) (UINTN) Address = Data;
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}
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else {
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UINT64 hwcrSave;
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hwcrSave = SetFsBase (Address);
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__writefsword (0, Data);
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RestoreHwcr (hwcrSave);
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}
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}
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AMDLIB_OPTIMIZE
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VOID
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Write64Mem32 (
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IN UINT64 Address,
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IN UINT32 Data
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)
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{
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if ((Address >> 32) == 0){
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*(volatile UINT32 *) (UINTN) Address = Data;
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}
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else {
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UINT64 hwcrSave;
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hwcrSave = SetFsBase (Address);
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__writefsdword (0, Data);
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RestoreHwcr (hwcrSave);
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}
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}
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AMDLIB_OPTIMIZE
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VOID
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LibAmdMsrRead (
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IN UINT32 MsrAddress,
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OUT UINT64 *Value,
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IN OUT AMD_CONFIG_PARAMS *ConfigPtr
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)
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{
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*Value = __readmsr (MsrAddress);
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}
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AMDLIB_OPTIMIZE
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VOID
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LibAmdMsrWrite (
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IN UINT32 MsrAddress,
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IN UINT64 *Value,
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IN OUT AMD_CONFIG_PARAMS *ConfigPtr
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)
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{
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__writemsr (MsrAddress, *Value);
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}
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/*---------------------------------------------------------------------------------------*/
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/**
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* Read IO port
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*
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*
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* @param[in] AccessWidth Access width
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* @param[in] IoAddress IO port address
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* @param[in] Value Pointer to save data
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* @param[in] StdHeader Standard configuration header
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*
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*/
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VOID
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LibAmdIoRead (
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IN ACCESS_WIDTH AccessWidth,
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IN UINT16 IoAddress,
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OUT VOID *Value,
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IN OUT AMD_CONFIG_PARAMS *StdHeader
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)
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{
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switch (AccessWidth) {
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case AccessWidth8:
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case AccessS3SaveWidth8:
|
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*(UINT8 *) Value = ReadIo8 (IoAddress);
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break;
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case AccessWidth16:
|
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case AccessS3SaveWidth16:
|
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*(UINT16 *) Value = ReadIo16 (IoAddress);
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break;
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case AccessWidth32:
|
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case AccessS3SaveWidth32:
|
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*(UINT32 *) Value = ReadIo32 (IoAddress);
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break;
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default:
|
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ASSERT (FALSE);
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break;
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}
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}
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|
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||||||
/*---------------------------------------------------------------------------------------*/
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|
||||||
/**
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||||||
* Write IO port
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*
|
|
||||||
*
|
|
||||||
* @param[in] AccessWidth Access width
|
|
||||||
* @param[in] IoAddress IO port address
|
|
||||||
* @param[in] Value Pointer to data
|
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||||||
* @param[in] StdHeader Standard configuration header
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
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LibAmdIoWrite (
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|
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IN ACCESS_WIDTH AccessWidth,
|
|
||||||
IN UINT16 IoAddress,
|
|
||||||
IN CONST VOID *Value,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
switch (AccessWidth) {
|
|
||||||
case AccessWidth8:
|
|
||||||
case AccessS3SaveWidth8:
|
|
||||||
WriteIo8 (IoAddress, *(UINT8 *) Value);
|
|
||||||
break;
|
|
||||||
case AccessWidth16:
|
|
||||||
case AccessS3SaveWidth16:
|
|
||||||
WriteIo16 (IoAddress, *(UINT16 *) Value);
|
|
||||||
break;
|
|
||||||
case AccessWidth32:
|
|
||||||
case AccessS3SaveWidth32:
|
|
||||||
WriteIo32 (IoAddress, *(UINT32 *) Value);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
ASSERT (FALSE);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* Read memory/MMIO
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] AccessWidth Access width
|
|
||||||
* @param[in] MemAddress Memory address
|
|
||||||
* @param[in] Value Pointer to data
|
|
||||||
* @param[in] StdHeader Standard configuration header
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
LibAmdMemRead (
|
|
||||||
IN ACCESS_WIDTH AccessWidth,
|
|
||||||
IN UINT64 MemAddress,
|
|
||||||
OUT VOID *Value,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
switch (AccessWidth) {
|
|
||||||
case AccessWidth8:
|
|
||||||
case AccessS3SaveWidth8:
|
|
||||||
*(UINT8 *) Value = Read64Mem8 (MemAddress);
|
|
||||||
break;
|
|
||||||
case AccessWidth16:
|
|
||||||
case AccessS3SaveWidth16:
|
|
||||||
*(UINT16 *) Value = Read64Mem16 (MemAddress);
|
|
||||||
break;
|
|
||||||
case AccessWidth32:
|
|
||||||
case AccessS3SaveWidth32:
|
|
||||||
*(UINT32 *) Value = Read64Mem32 (MemAddress);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
ASSERT (FALSE);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* Write memory/MMIO
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] AccessWidth Access width
|
|
||||||
* @param[in] MemAddress Memory address
|
|
||||||
* @param[in] Value Pointer to data
|
|
||||||
* @param[in] StdHeader Standard configuration header
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
LibAmdMemWrite (
|
|
||||||
IN ACCESS_WIDTH AccessWidth,
|
|
||||||
IN UINT64 MemAddress,
|
|
||||||
IN CONST VOID *Value,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
|
|
||||||
switch (AccessWidth) {
|
|
||||||
case AccessWidth8:
|
|
||||||
case AccessS3SaveWidth8:
|
|
||||||
Write64Mem8 (MemAddress, *((UINT8 *) Value));
|
|
||||||
break;
|
|
||||||
case AccessWidth16:
|
|
||||||
case AccessS3SaveWidth16:
|
|
||||||
Write64Mem16 (MemAddress, *((UINT16 *) Value));
|
|
||||||
break;
|
|
||||||
case AccessWidth32:
|
|
||||||
case AccessS3SaveWidth32:
|
|
||||||
Write64Mem32 (MemAddress, *((UINT32 *) Value));
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
ASSERT (FALSE);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* Read PCI config space
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] AccessWidth Access width
|
|
||||||
* @param[in] PciAddress Pci address
|
|
||||||
* @param[in] Value Pointer to data
|
|
||||||
* @param[in] StdHeader Standard configuration header
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
LibAmdPciRead (
|
|
||||||
IN ACCESS_WIDTH AccessWidth,
|
|
||||||
IN PCI_ADDR PciAddress,
|
|
||||||
OUT VOID *Value,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 LegacyPciAccess;
|
|
||||||
UINT32 MMIOSize;
|
|
||||||
UINT64 RMWrite;
|
|
||||||
UINT64 RMWritePrevious;
|
|
||||||
UINT64 MMIOAddress;
|
|
||||||
|
|
||||||
|
|
||||||
ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO);
|
|
||||||
if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, NULL)) {
|
|
||||||
// We need to convert our "portable" PCI address into a "real" PCI access
|
|
||||||
LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8)));
|
|
||||||
if (PciAddress.Address.Register <= 0xFF) {
|
|
||||||
LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, NULL);
|
|
||||||
LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, NULL);
|
|
||||||
} else {
|
|
||||||
LibAmdMsrRead (NB_CFG, &RMWritePrevious, NULL);
|
|
||||||
RMWrite = RMWritePrevious | 0x0000400000000000;
|
|
||||||
LibAmdMsrWrite (NB_CFG, &RMWrite, NULL);
|
|
||||||
LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, NULL);
|
|
||||||
LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, NULL);
|
|
||||||
LibAmdMsrWrite (NB_CFG, &RMWritePrevious, NULL);
|
|
||||||
}
|
|
||||||
//IDS_HDT_CONSOLE (LIB_PCI_RD, "~PCI RD %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
|
|
||||||
} else {
|
|
||||||
// Setup the MMIO address
|
|
||||||
ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF)));
|
|
||||||
MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF);
|
|
||||||
LibAmdMemRead (AccessWidth, MMIOAddress, Value, NULL);
|
|
||||||
//IDS_HDT_CONSOLE (LIB_PCI_RD, "~MMIO RD %08x = %08x\n", (UINT32) MMIOAddress, *(UINT32 *)Value);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* Write PCI config space
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* @param[in] AccessWidth Access width
|
|
||||||
* @param[in] PciAddress Pci address
|
|
||||||
* @param[in] Value Pointer to data
|
|
||||||
* @param[in] StdHeader Standard configuration header
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
LibAmdPciWrite (
|
|
||||||
IN ACCESS_WIDTH AccessWidth,
|
|
||||||
IN PCI_ADDR PciAddress,
|
|
||||||
IN CONST VOID *Value,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 LegacyPciAccess;
|
|
||||||
UINT32 MMIOSize;
|
|
||||||
UINT64 RMWrite;
|
|
||||||
UINT64 RMWritePrevious;
|
|
||||||
UINT64 MMIOAddress;
|
|
||||||
|
|
||||||
|
|
||||||
ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO);
|
|
||||||
if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, NULL)) {
|
|
||||||
// We need to convert our "portable" PCI address into a "real" PCI access
|
|
||||||
LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8)));
|
|
||||||
if (PciAddress.Address.Register <= 0xFF) {
|
|
||||||
LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, NULL);
|
|
||||||
LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, NULL);
|
|
||||||
} else {
|
|
||||||
LibAmdMsrRead (NB_CFG, &RMWritePrevious, NULL);
|
|
||||||
RMWrite = RMWritePrevious | 0x0000400000000000;
|
|
||||||
LibAmdMsrWrite (NB_CFG, &RMWrite, NULL);
|
|
||||||
LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, NULL);
|
|
||||||
LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, NULL);
|
|
||||||
LibAmdMsrWrite (NB_CFG, &RMWritePrevious, NULL);
|
|
||||||
}
|
|
||||||
//IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
|
|
||||||
//printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
|
|
||||||
//printk(BIOS_DEBUG, "LibAmdPciWrite\n");
|
|
||||||
} else {
|
|
||||||
// Setup the MMIO address
|
|
||||||
ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF)));
|
|
||||||
MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF);
|
|
||||||
LibAmdMemWrite (AccessWidth, MMIOAddress, Value, NULL);
|
|
||||||
//IDS_HDT_CONSOLE (LIB_PCI_WR, "~MMIO WR %08x = %08x\n", (UINT32) MMIOAddress, *(UINT32 *)Value);
|
|
||||||
//printk(BIOS_DEBUG, "~MMIO WR %08x = %08x\n", (UINT32) MMIOAddress, *(UINT32 *)Value);
|
|
||||||
//printk(BIOS_DEBUG, "LibAmdPciWrite mmio\n");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* Get MMIO base address for PCI accesses
|
|
||||||
*
|
|
||||||
* @param[out] MmioAddress PCI MMIO base address
|
|
||||||
* @param[out] MmioSize Size of region in bytes
|
|
||||||
* @param[in] StdHeader Standard configuration header
|
|
||||||
*
|
|
||||||
* @retval TRUE MmioAddress/MmioSize are valid
|
|
||||||
*/
|
|
||||||
BOOLEAN
|
|
||||||
STATIC
|
|
||||||
GetPciMmioAddress (
|
|
||||||
OUT UINT64 *MmioAddress,
|
|
||||||
OUT UINT32 *MmioSize,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
BOOLEAN MmioIsEnabled;
|
|
||||||
UINT32 EncodedSize;
|
|
||||||
UINT64 LocalMsrRegister;
|
|
||||||
|
|
||||||
MmioIsEnabled = FALSE;
|
|
||||||
LibAmdMsrRead (MSR_MMIO_Cfg_Base, &LocalMsrRegister, NULL);
|
|
||||||
if ((LocalMsrRegister & BIT0) != 0) {
|
|
||||||
*MmioAddress = LocalMsrRegister & 0xFFFFFFFFFFF00000;
|
|
||||||
EncodedSize = (UINT32) ((LocalMsrRegister & 0x3C) >> 2);
|
|
||||||
*MmioSize = ((1 << EncodedSize) * 0x100000);
|
|
||||||
MmioIsEnabled = TRUE;
|
|
||||||
}
|
|
||||||
return MmioIsEnabled;
|
|
||||||
}
|
|
||||||
|
|
@ -1,202 +0,0 @@
|
||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* AMD Library
|
|
||||||
*
|
|
||||||
* Contains interface to the AMD AGESA library
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: Lib
|
|
||||||
* @e \$Revision: 85030 $ @e \$Date: 2012-12-26 00:20:10 -0600 (Wed, 26 Dec 2012) $
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*
|
|
||||||
******************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
|
|
||||||
* 2013 - 2014, Sage Electronic Engineering, LLC
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
******************************************************************************
|
|
||||||
**/
|
|
||||||
|
|
||||||
#ifndef _AMD_LIB_H_
|
|
||||||
#define _AMD_LIB_H_
|
|
||||||
|
|
||||||
#include <agesa_headers.h>
|
|
||||||
|
|
||||||
#define IOCF8 0xCF8
|
|
||||||
#define IOCFC 0xCFC
|
|
||||||
|
|
||||||
// Reg Values for ReadCpuReg and WriteCpuReg
|
|
||||||
#define CR4_REG 0x04
|
|
||||||
#define DR0_REG 0x10
|
|
||||||
#define DR1_REG 0x11
|
|
||||||
#define DR2_REG 0x12
|
|
||||||
#define DR3_REG 0x13
|
|
||||||
#define DR7_REG 0x17
|
|
||||||
|
|
||||||
// PROTOTYPES FOR amdlib32.asm
|
|
||||||
UINT8
|
|
||||||
ReadIo8 (
|
|
||||||
IN UINT16 Address
|
|
||||||
);
|
|
||||||
|
|
||||||
UINT16
|
|
||||||
ReadIo16 (
|
|
||||||
IN UINT16 Address
|
|
||||||
);
|
|
||||||
|
|
||||||
UINT32
|
|
||||||
ReadIo32 (
|
|
||||||
IN UINT16 Address
|
|
||||||
);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
WriteIo8 (
|
|
||||||
IN UINT16 Address,
|
|
||||||
IN UINT8 Data
|
|
||||||
);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
WriteIo16 (
|
|
||||||
IN UINT16 Address,
|
|
||||||
IN UINT16 Data
|
|
||||||
);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
WriteIo32 (
|
|
||||||
IN UINT16 Address,
|
|
||||||
IN UINT32 Data
|
|
||||||
);
|
|
||||||
|
|
||||||
UINT8
|
|
||||||
Read64Mem8 (
|
|
||||||
IN UINT64 Address
|
|
||||||
);
|
|
||||||
|
|
||||||
UINT16
|
|
||||||
Read64Mem16 (
|
|
||||||
IN UINT64 Address
|
|
||||||
);
|
|
||||||
|
|
||||||
UINT32
|
|
||||||
Read64Mem32 (
|
|
||||||
IN UINT64 Address
|
|
||||||
);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
Write64Mem8 (
|
|
||||||
IN UINT64 Address,
|
|
||||||
IN UINT8 Data
|
|
||||||
);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
Write64Mem16 (
|
|
||||||
IN UINT64 Address,
|
|
||||||
IN UINT16 Data
|
|
||||||
);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
Write64Mem32 (
|
|
||||||
IN UINT64 Address,
|
|
||||||
IN UINT32 Data
|
|
||||||
);
|
|
||||||
|
|
||||||
// MSR
|
|
||||||
VOID
|
|
||||||
LibAmdMsrRead (
|
|
||||||
IN UINT32 MsrAddress,
|
|
||||||
OUT UINT64 *Value,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
LibAmdMsrWrite (
|
|
||||||
IN UINT32 MsrAddress,
|
|
||||||
IN UINT64 *Value,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
// IO
|
|
||||||
VOID
|
|
||||||
LibAmdIoRead (
|
|
||||||
IN ACCESS_WIDTH AccessWidth,
|
|
||||||
IN UINT16 IoAddress,
|
|
||||||
OUT VOID *Value,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
LibAmdIoWrite (
|
|
||||||
IN ACCESS_WIDTH AccessWidth,
|
|
||||||
IN UINT16 IoAddress,
|
|
||||||
IN CONST VOID *Value,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
// Memory or MMIO
|
|
||||||
VOID
|
|
||||||
LibAmdMemRead (
|
|
||||||
IN ACCESS_WIDTH AccessWidth,
|
|
||||||
IN UINT64 MemAddress,
|
|
||||||
OUT VOID *Value,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
LibAmdMemWrite (
|
|
||||||
IN ACCESS_WIDTH AccessWidth,
|
|
||||||
IN UINT64 MemAddress,
|
|
||||||
IN CONST VOID *Value,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
// PCI
|
|
||||||
VOID
|
|
||||||
LibAmdPciRead (
|
|
||||||
IN ACCESS_WIDTH AccessWidth,
|
|
||||||
IN PCI_ADDR PciAddress,
|
|
||||||
OUT VOID *Value,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
LibAmdPciWrite (
|
|
||||||
IN ACCESS_WIDTH AccessWidth,
|
|
||||||
IN PCI_ADDR PciAddress,
|
|
||||||
IN CONST VOID *Value,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
// CPUID
|
|
||||||
VOID
|
|
||||||
LibAmdCpuidRead (
|
|
||||||
IN UINT32 CpuidFcnAddress,
|
|
||||||
OUT CPUID_DATA *Value,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
#endif // _AMD_LIB_H_
|
|
||||||
|
|
@ -108,7 +108,6 @@
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include "Fch.h"
|
#include "Fch.h"
|
||||||
#include "amdlib.h"
|
|
||||||
#include "FchCommonCfg.h"
|
#include "FchCommonCfg.h"
|
||||||
#include "AmdFch.h"
|
#include "AmdFch.h"
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue